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cb31fcd0db
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Configurable [l,s]w[l,r]
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2022-08-04 20:25:43 +08:00 |
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796c83b72a
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adjust mul/div
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2022-08-04 19:54:40 +08:00 |
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8db46ab67b
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fix DCache
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2022-08-04 18:41:16 +08:00 |
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dfa2e628a2
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Minimize CP0 when TLB is disabled
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2022-08-04 16:43:29 +08:00 |
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baa2bb049f
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Configurable MADD
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2022-08-04 16:15:18 +08:00 |
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acc50f3c89
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fix bug
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2022-08-04 15:14:07 +08:00 |
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31030d6a84
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Configurable Cache
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2022-08-04 14:44:31 +08:00 |
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bab898db60
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Config1 auto generate
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2022-08-04 13:24:45 +08:00 |
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d31446ae87
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Configurable Cache & Bigger Cache
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2022-08-04 13:00:33 +08:00 |
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d487e8583d
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Update ENABLE_TLB
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2022-08-04 11:53:11 +08:00 |
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02f04a2bf3
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Update MU and DCache
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2022-08-03 14:26:44 +08:00 |
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db1aa1d615
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Manual Merge
Co-authored-by: cxy004 <cxy004@qq.com>
Co-authored-by: Hooo1941 <Hooo1941@users.noreply.github.com>
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2022-08-02 11:29:23 +08:00 |
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a7793c6741
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Another big update
1. refactor func test
2. fix CACHE inst
3. CP0 add Context Register
4. fix AXIWriter order
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2022-08-01 22:01:24 +08:00 |
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56cc2e5dcb
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fix: MU wstrb could directly passthrough
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2022-07-29 23:25:14 +08:00 |
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b25fbb5ee1
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fix: multiply model
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2022-07-29 18:48:58 +08:00 |
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bf7ee46645
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feat: reconfigure crossbar
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2022-07-29 18:26:27 +08:00 |
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7b33e4213a
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a big update
1. add test soft
2. modify verilator (TODO: crossbar need to replace)
3. fix CP0: now CU0 is always 1
4. Controller: cacheop
5. Controller: fix TEN
6. mycpu_top fix CP0_i
7. fix AXI.sv
8. fix AXIReader.sv
9. fix AXIWriter.sv: getting the correct data and length
10. MU: fix cache writeback, fix mem data mux, fix writer address, fix read request
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2022-07-29 18:25:58 +08:00 |
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4f7fe2adf2
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feat: MU rewrite 2
TLB Support
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2022-07-27 18:11:54 +08:00 |
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9ce588757d
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feat: MU rewrite 1
1. ALU format
2. FIX hazard (MOVN / MOVZ)
3. verilator support
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2022-07-27 15:07:16 +08:00 |
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Qiu Jiahao
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e569965556
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refactor MU
Co-authored-by: Paul <panyuxuan@hotmail.com>
Co-authored-by: cxy004 <cxy004@qq.com>
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2022-07-16 08:44:29 +08:00 |
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Qiu Jiahao
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eb9f835e6b
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refactor cache
Co-authored-by: cxy004 <cxy004@qq.com>
Co-authored-by: Paul <panyuxuan@hotmail.com>
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2022-06-21 21:52:06 +08:00 |
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b3238b0f86
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Merge branch 'soc_top'
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2022-05-24 21:51:02 +08:00 |
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a2f8fdae9b
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clean up
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2021-10-14 22:31:25 +08:00 |
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00170784d0
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Merge branch 'fix/cache' into soc_top
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2021-10-14 22:20:31 +08:00 |
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24613eeade
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Revert "refactor DCache"
This reverts commit fa0f195d17 .
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2021-09-30 22:48:27 +08:00 |
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fa0f195d17
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refactor DCache
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2021-09-30 22:45:28 +08:00 |
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c4942661dc
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refactor cache inst on I-Cache
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2021-09-27 16:58:22 +08:00 |
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4facc2dd10
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enhanced test cases
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2021-09-24 20:45:55 +08:00 |
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aca8490ef2
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deal with verilator
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2021-09-24 16:37:47 +08:00 |
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8c7272e1f2
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add model
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2021-09-22 23:07:13 +08:00 |
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a5192eb4d8
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update README.md
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2021-09-22 22:29:52 +08:00 |
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62b26e3ab2
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fix trap
add testcases
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2021-09-22 16:26:40 +08:00 |
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de354f73d0
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fix Datapath.sv
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2021-09-22 13:52:43 +08:00 |
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75a62cfc37
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try add trap
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2021-09-22 13:41:09 +08:00 |
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a1bbfa0a0c
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make linter happy
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2021-09-21 17:15:30 +08:00 |
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ab1b2ad13d
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fix CP0
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2021-09-12 19:48:56 +08:00 |
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a0d3367f34
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update ALU and test
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2021-09-07 19:53:53 +08:00 |
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29c6e16682
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try add MOVZ, MOVN
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2021-09-07 19:24:34 +08:00 |
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7e85ca17e3
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refactor D-Cache CACHE inst
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2021-09-06 22:36:37 +08:00 |
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0cd3d9007e
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1. fix D-Cache clear by index
2. fix testcases
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2021-09-06 09:27:22 +08:00 |
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9df689ed7a
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refactor CACHE inst on D-CACHE
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2021-09-05 23:59:23 +08:00 |
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f8d7b7b0c6
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1. fix exceptions about CACHE inst on D-Cache
2. fix D-Cache control signals
3. fix I-Cache tag1 signal
4. fix I-Cache clear index logic
5. enhance D-Cache tests
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2021-09-05 13:06:35 +08:00 |
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1f2d7f6f3c
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1. fix deadlock on continuous CACHE inst
2. enhance the testcases
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2021-09-04 21:07:00 +08:00 |
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e08ded2242
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Test Passed? maybe
1. fix timing loop
2. fix multi driven
3. fix CACHE I-Cache Index logic
4. fix testcase
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2021-09-04 16:31:25 +08:00 |
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fa0c8ece07
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1. fix index addr
2. add n99 I-Cache CACHE test
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2021-09-03 22:16:59 +08:00 |
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2143cbe630
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try add I-Cache's CACHE inst
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2021-09-03 21:23:32 +08:00 |
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17f64e1f2f
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1. add cache (D-Cache Address) inst
2. fix bug in ALR
3. fix bug in MMU and DCache
4. Register File rst
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2021-09-02 19:20:19 +08:00 |
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f256abd248
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add control signals
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2021-09-02 19:05:23 +08:00 |
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ed49e734d8
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update Controller and Datapath
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2021-09-02 11:05:33 +08:00 |
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3dffdae575
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try add D-Cache's CACHE inst
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2021-09-01 23:12:58 +08:00 |
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