.vscode | ||
resources | ||
src | ||
tools | ||
.editorconfig | ||
.gitignore | ||
README.md |
Magically Improved Pipeline Stages
Our awesome MIPS
CPU written in SystemVerilog
for Loongson Cup
.
├── resources <-- 资源包
├── src <-- CPU设计代码
│ ├── AXI <-- AXI总线交互
│ ├── Cache <-- Cache
│ ├── Core <-- CPU核心
│ ├── CP0 <-- CP0协处理器
│ ├── include <-- 头文件
│ ├── IP <-- 用到的IP
│ └── MMU <-- 地址转换单元
└── tools <-- 控制信号生成器
Progress
- 特权模式
CP0
寄存器Status.UM
✔️- 访存异常(考虑
in_kernel
状态切换带来的冒险) ✔️ - 特权指令异常 ✔️
- 浮点运算单元
做一个真的❌FPU
- 浮点运算指令报
Coprocessor Unusable
,同时CP0
中新增Cause.CE
🕒
- 新增指令
Status | Instruction | Type | Tier | Comment |
---|---|---|---|---|
⌛ | I-Cache Index Invalid |
SYS |
2 | |
⌛ | I-Cache Hit Invalid |
SYS |
2 | |
⌛ | D-Cache Index Writeback Invalid |
SYS |
2 | |
⌛ | D-Cache Index Store Tag |
SYS |
2 | |
⌛ | D-Cache Hit Invalid |
SYS |
2 | |
⌛ | D-Cache Hit Writeback Invalid |
SYS |
2 | |
✔️ | PREF |
SYS |
1 | Treat as NOP |
✔️ | SYNC |
SYS |
1 | Treat as NOP (We're strongly ordered) |
🕒 | WAIT |
SYS |
2 | |
🕒 | TEQ |
SYS |
2 | |
🕒 | TEQI |
SYS |
2 | |
🕒 | TGE |
SYS |
2 | |
🕒 | TGEI |
SYS |
2 | |
🕒 | TGEIU |
SYS |
2 | |
🕒 | TGEU |
SYS |
2 | |
🕒 | TLT |
SYS |
2 | |
🕒 | TLTI |
SYS |
2 | |
🕒 | TLTIU |
SYS |
2 | |
🕒 | TLTU |
SYS |
2 | |
🕒 | TNE |
SYS |
2 | |
🕒 | TNEI |
SYS |
2 | |
🕒 | CLO |
ARITH |
2 | RT == RD |
🕒 | CLZ |
ARITH |
2 | RT == RD |
✔️ | MADD |
ARITH |
2 | M 阶段加一个流水级 |
✔️ | MADDU |
ARITH |
2 | M 阶段加一个流水级 |
✔️ | MSUB |
ARITH |
2 | M 阶段加一个流水级 |
✔️ | MSUBU |
ARITH |
2 | M 阶段加一个流水级 |
⌛ | MOVN |
ARITH |
2 | D 阶段阻塞 |
⌛ | MOVZ |
ARITH |
2 | D 阶段阻塞 |
❌ | LL |
MEM |
3 | 修改内核去除相关指令 |
✔️ | LWL |
MEM |
1 | |
✔️ | LWR |
MEM |
1 | |
❌ | SC |
MEM |
3 | 修改内核去除相关指令 |
✔️ | SWL |
MEM |
1 | |
✔️ | SWR |
MEM |
1 | |
🕒 | MOVF |
FP |
3 | |
🕒 | MOVT |
FP |
3 | |
❌ | BEQL |
BRANCH |
3 | 修改编译指令 |
❌ | BGEZALL |
BRANCH |
3 | 修改编译指令 |
❌ | BGEZL |
BRANCH |
3 | 修改编译指令 |
❌ | BGTZL |
BRANCH |
3 | 修改编译指令 |
❌ | BLEZL |
BRANCH |
3 | 修改编译指令 |
❌ | BLTZALL |
BRANCH |
3 | 修改编译指令 |
❌ | BLTZL |
BRANCH |
3 | 修改编译指令 |
❌ | BNEL |
BRANCH |
3 | 修改编译指令 |
Cache
指令
预计实现以下7
条操作
32'b101111?????00000???????????????? // I-Cache Index Invalid
32'b101111?????01000???????????????? // I-Cache Index Store Tag
32'b101111?????10000???????????????? // I-Cache Hit Invalid
32'b101111?????00001???????????????? // D-Cache Index Writeback Invalid
32'b101111?????01001???????????????? // D-Cache Index Store Tag
32'b101111?????10001???????????????? // D-Cache Hit Invalid
32'b101111?????10101???????????????? // D-Cache Hit Writeback Invalid
其中,Index Store Tag
中使用到了TagLo
和TagHi
寄存器。考虑到地址最多32
位,故不实现TagHi
寄存器(恒0
);同时,由于TagLo
和TagHi
寄存器定义与具体处理器实现相关,在应用上用于将Cache
的Tag
清零(可以魔改内核),故也不实现TagLo
寄存器(恒0
)。所以Index Store Tag
指令在实现上变为不写回的Index Invalid
对于上述操作,具体实现:
Cache -> VIPT
Index Invalid : VA -> Index -> (Write Back) -> Write Zero
Index Store Tag : VA -> Index -> Write Zero
Hit Invalid : VA -> Lookup -> Hit? -> Write Zero
Hit Writeback Invalid : VA -> Lookup -> Hit? -> (Write Back) -> Write Zero
控制信号:
CacheOp[2] |
CacheOp[1] |
CacheOp[0] |
Name |
---|---|---|---|
0 | 0 | 0 | NOP |
0 | 0 | 1 | |
0 | 1 | ? | |
1 | 0 | 0 | |
1 | 0 | 1 | |
1 | 1 | 0 | |
1 | 1 | 1 | |
I-Cache(0) or D-Cache(1) |
Lookup(0) or Index(1) |
WriteBack(0) or WriteOnly(1) |
备注:
Cache
指令当成写请求