try add D-Cache's CACHE inst
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README.md
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README.md
@ -28,46 +28,94 @@ Our awesome `MIPS` CPU written in `SystemVerilog` for Loongson Cup
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- [ ] 浮点运算指令报`Coprocessor Unusable`，同时`CP0`中新增`Cause.CE` :clock3:
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- [ ] 新增指令
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| Status | Instruction | Type | Tier | Comment |
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| :----------------: | :---------: | :------: | :--: | :-------------------------------------- |
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| :hourglass: | `Cache` | `SYS` | 2 | |
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| :heavy_check_mark: | `PREF` | `SYS` | 1 | Treat as `NOP` |
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| :heavy_check_mark: | `SYNC` | `SYS` | 1 | Treat as `NOP` (We're strongly ordered) |
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| :clock3: | `WAIT` | `SYS` | 2 | |
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| :clock3: | `TEQ` | `SYS` | 2 | |
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| :clock3: | `TEQI` | `SYS` | 2 | |
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| :clock3: | `TGE` | `SYS` | 2 | |
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| :clock3: | `TGEI` | `SYS` | 2 | |
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| :clock3: | `TGEIU` | `SYS` | 2 | |
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| :clock3: | `TGEU` | `SYS` | 2 | |
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| :clock3: | `TLT` | `SYS` | 2 | |
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| :clock3: | `TLTI` | `SYS` | 2 | |
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| :clock3: | `TLTIU` | `SYS` | 2 | |
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| :clock3: | `TLTU` | `SYS` | 2 | |
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| :clock3: | `TNE` | `SYS` | 2 | |
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| :clock3: | `TNEI` | `SYS` | 2 | |
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| :clock3: | `CLO` | `ARITH` | 2 | `RT == RD` |
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| :clock3: | `CLZ` | `ARITH` | 2 | `RT == RD` |
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| :hourglass: | `MADD` | `ARITH` | 2 | `M`阶段加一个流水级 |
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| :hourglass: | `MADDU` | `ARITH` | 2 | `M`阶段加一个流水级 |
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| :hourglass: | `MSUB` | `ARITH` | 2 | `M`阶段加一个流水级 |
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| :hourglass: | `MSUBU` | `ARITH` | 2 | `M`阶段加一个流水级 |
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| :hourglass: | `MOVN` | `ARITH` | 2 | `D`阶段阻塞 |
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| :hourglass: | `MOVZ` | `ARITH` | 2 | `D`阶段阻塞 |
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| :x: | `LL` | `MEM` | 3 | 修改内核去除相关指令 |
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| :heavy_check_mark: | `LWL` | `MEM` | 1 | |
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| :heavy_check_mark: | `LWR` | `MEM` | 1 | |
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| :x: | `SC` | `MEM` | 3 | 修改内核去除相关指令 |
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| :heavy_check_mark: | `SWL` | `MEM` | 1 | |
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| :heavy_check_mark: | `SWR` | `MEM` | 1 | |
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| :clock3: | `MOVF` | `FP` | 3 | |
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| :clock3: | `MOVT` | `FP` | 3 | |
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| :x: | `BEQL` | `BRANCH` | 3 | 修改编译指令 |
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| :x: | `BGEZALL` | `BRANCH` | 3 | 修改编译指令 |
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| :x: | `BGEZL` | `BRANCH` | 3 | 修改编译指令 |
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| :x: | `BGTZL` | `BRANCH` | 3 | 修改编译指令 |
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| :x: | `BLEZL` | `BRANCH` | 3 | 修改编译指令 |
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| :x: | `BLTZALL` | `BRANCH` | 3 | 修改编译指令 |
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| :x: | `BLTZL` | `BRANCH` | 3 | 修改编译指令 |
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| :x: | `BNEL` | `BRANCH` | 3 | 修改编译指令 |
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| Status | Instruction | Type | Tier | Comment |
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| :----------------: | :-------------------------------: | :------: | :--: | :-------------------------------------- |
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| :hourglass: | `I-Cache Index Invalid` | `SYS` | 2 | |
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| :hourglass: | `I-Cache Hit Invalid` | `SYS` | 2 | |
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| :hourglass: | `D-Cache Index Writeback Invalid` | `SYS` | 2 | |
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| :hourglass: | `D-Cache Index Store Tag` | `SYS` | 2 | |
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| :hourglass: | `D-Cache Hit Invalid` | `SYS` | 2 | |
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| :hourglass: | `D-Cache Hit Writeback Invalid` | `SYS` | 2 | |
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| :heavy_check_mark: | `PREF` | `SYS` | 1 | Treat as `NOP` |
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| :heavy_check_mark: | `SYNC` | `SYS` | 1 | Treat as `NOP` (We're strongly ordered) |
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| :clock3: | `WAIT` | `SYS` | 2 | |
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| :clock3: | `TEQ` | `SYS` | 2 | |
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| :clock3: | `TEQI` | `SYS` | 2 | |
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| :clock3: | `TGE` | `SYS` | 2 | |
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| :clock3: | `TGEI` | `SYS` | 2 | |
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| :clock3: | `TGEIU` | `SYS` | 2 | |
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| :clock3: | `TGEU` | `SYS` | 2 | |
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| :clock3: | `TLT` | `SYS` | 2 | |
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| :clock3: | `TLTI` | `SYS` | 2 | |
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| :clock3: | `TLTIU` | `SYS` | 2 | |
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| :clock3: | `TLTU` | `SYS` | 2 | |
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| :clock3: | `TNE` | `SYS` | 2 | |
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| :clock3: | `TNEI` | `SYS` | 2 | |
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| :clock3: | `CLO` | `ARITH` | 2 | `RT == RD` |
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| :clock3: | `CLZ` | `ARITH` | 2 | `RT == RD` |
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| :heavy_check_mark: | `MADD` | `ARITH` | 2 | `M`阶段加一个流水级 |
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| :heavy_check_mark: | `MADDU` | `ARITH` | 2 | `M`阶段加一个流水级 |
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| :heavy_check_mark: | `MSUB` | `ARITH` | 2 | `M`阶段加一个流水级 |
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| :heavy_check_mark: | `MSUBU` | `ARITH` | 2 | `M`阶段加一个流水级 |
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| :hourglass: | `MOVN` | `ARITH` | 2 | `D`阶段阻塞 |
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| :hourglass: | `MOVZ` | `ARITH` | 2 | `D`阶段阻塞 |
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| :x: | `LL` | `MEM` | 3 | 修改内核去除相关指令 |
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| :heavy_check_mark: | `LWL` | `MEM` | 1 | |
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| :heavy_check_mark: | `LWR` | `MEM` | 1 | |
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| :x: | `SC` | `MEM` | 3 | 修改内核去除相关指令 |
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| :heavy_check_mark: | `SWL` | `MEM` | 1 | |
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| :heavy_check_mark: | `SWR` | `MEM` | 1 | |
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| :clock3: | `MOVF` | `FP` | 3 | |
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| :clock3: | `MOVT` | `FP` | 3 | |
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| :x: | `BEQL` | `BRANCH` | 3 | 修改编译指令 |
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| :x: | `BGEZALL` | `BRANCH` | 3 | 修改编译指令 |
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| :x: | `BGEZL` | `BRANCH` | 3 | 修改编译指令 |
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| :x: | `BGTZL` | `BRANCH` | 3 | 修改编译指令 |
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| :x: | `BLEZL` | `BRANCH` | 3 | 修改编译指令 |
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| :x: | `BLTZALL` | `BRANCH` | 3 | 修改编译指令 |
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| :x: | `BLTZL` | `BRANCH` | 3 | 修改编译指令 |
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| :x: | `BNEL` | `BRANCH` | 3 | 修改编译指令 |
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## `Cache`指令
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预计实现以下`7`条操作
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```verilog
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32'b101111?????00000???????????????? // I-Cache Index Invalid
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32'b101111?????01000???????????????? // I-Cache Index Store Tag
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32'b101111?????10000???????????????? // I-Cache Hit Invalid
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32'b101111?????00001???????????????? // D-Cache Index Writeback Invalid
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32'b101111?????01001???????????????? // D-Cache Index Store Tag
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32'b101111?????10001???????????????? // D-Cache Hit Invalid
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32'b101111?????10101???????????????? // D-Cache Hit Writeback Invalid
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```
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其中，`Index Store Tag`中使用到了`TagLo`和`TagHi`寄存器。考虑到地址最多`32`位，故不实现`TagHi`寄存器(恒`0`)；同时，由于`TagLo`和`TagHi`寄存器定义与具体处理器实现相关，在应用上用于将`Cache`的`Tag`清零（可以魔改内核），故也不实现`TagLo`寄存器(恒`0`)。所以`Index Store Tag`指令在实现上变为不写回的`Index Invalid`
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对于上述操作，具体实现：
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```
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Cache -> VIPT
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Index Invalid : VA -> Index -> (Write Back) -> Write Zero
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Index Store Tag : VA -> Index -> Write Zero
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Hit Invalid : VA -> Lookup -> Hit? -> Write Zero
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Hit Writeback Invalid : VA -> Lookup -> Hit? -> (Write Back) -> Write Zero
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```
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控制信号：
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| `CacheOp[2]` | `CacheOp[1]` | `CacheOp[0]` | Name |
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| :------------------------: | :---------------------: | :----------------------------: | :---: |
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| 0 | 0 | 0 | `NOP` |
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| 0 | 0 | 1 | |
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| 0 | 1 | ? | |
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| 1 | 0 | 0 | |
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| 1 | 0 | 1 | |
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| 1 | 1 | 0 | |
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| 1 | 1 | 1 | |
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| `I-Cache(0) or D-Cache(1)` | `Lookup(0) or Index(1)` | `WriteBack(0) or WriteOnly(1)` | |
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备注：
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1. `Cache`指令当成写请求
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2.
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@ -45,7 +45,6 @@ module CP0 (
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& |{rf_cp0.Cause.IP & rf_cp0.Status.IM,
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rf_cp0.Cause.TI & rf_cp0.Status.IM[7]};
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assign rf_cp0.TagLo.zero = 9'b0;
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assign rf_cp0.Config.M = 1'b1;
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assign rf_cp0.Config.zero = 15'b0;
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assign rf_cp0.Config.BE = 1'b0;
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@ -88,9 +87,6 @@ module CP0 (
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always_ff @(posedge clk)
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if (rst) begin
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rf_cp0.TagLo.Tag = 21'b0;
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rf_cp0.TagLo.D = 1'b0;
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rf_cp0.TagLo.V = 1'b0;
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rf_cp0.Config.K0 = 3'b011;
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rf_cp0.EPC = 32'h0;
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rf_cp0.Cause.BD = 1'b0;
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@ -135,11 +131,7 @@ module CP0 (
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// 31: rf_cp0.DESAVE = wdata;
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// 30: rf_cp0.ErrorEPC = wdata;
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// 29: rf_cp0.TagHi = wdata;
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28: begin
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rf_cp0.TagLo.Tag = wdata[22:2];
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rf_cp0.TagLo.D = wdata[1];
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rf_cp0.TagLo.V = wdata[0];
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end
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// 28: rf_cp0.TagLo = wdata;
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// 27: rf_cp0.CacheErr = wdata;
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// 26: rf_cp0.Errctl = wdata;
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// 25: rf_cp0.PerfCnt = wdata;
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@ -257,7 +249,7 @@ module CP0 (
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// 31: rdata = rf_cp0.DESAVE;
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// 30: rdata = rf_cp0.ErrorEPC;
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// 29: rdata = rf_cp0.TagHi;
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28: rdata = rf_cp0.TagLo;
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// 28: rdata = rf_cp0.TagLo;
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// 27: rdata = rf_cp0.CacheErr;
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// 26: rdata = rf_cp0.Errctl;
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// 25: rdata = rf_cp0.PerfCnt;
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@ -240,10 +240,10 @@ module DCache (
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assign DataRAM2.wen = (bwe1 & wen[2]) | (bwe2 & wen2[2]);
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assign DataRAM3.wen = (bwe1 & wen[3]) | (bwe2 & wen2[3]);
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// 写数据
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assign TagRAM0.wdata = {port.tag1, port.wvalid, 1'b1};
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assign TagRAM1.wdata = {port.tag1, port.wvalid, 1'b1};
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assign TagRAM2.wdata = {port.tag1, port.wvalid, 1'b1};
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assign TagRAM3.wdata = {port.tag1, port.wvalid, 1'b1};
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assign TagRAM0.wdata = port.clear ? `DC_TAG_LENGTH'b0 : {port.tag1, port.wvalid, 1'b1};
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assign TagRAM1.wdata = port.clear ? `DC_TAG_LENGTH'b0 : {port.tag1, port.wvalid, 1'b1};
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assign TagRAM2.wdata = port.clear ? `DC_TAG_LENGTH'b0 : {port.tag1, port.wvalid, 1'b1};
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assign TagRAM3.wdata = port.clear ? `DC_TAG_LENGTH'b0 : {port.tag1, port.wvalid, 1'b1};
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assign DataRAM0.wdata = state == LOOKUP ? wdata1[0] : wdata2[0];
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assign DataRAM1.wdata = state == LOOKUP ? wdata1[1] : wdata2[1];
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@ -90,14 +90,14 @@ module instr_valid (
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32'b101010??????????????????????????: valid = 1'b1; // SWL
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32'b101011??????????????????????????: valid = 1'b1; // SW
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32'b101110??????????????????????????: valid = 1'b1; // SWR
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32'b101111?????00000????????????????: valid = 1'b1; // I-Cache Index Invalid
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32'b101111?????01000????????????????: valid = 1'b1; // I-Cache Index Store Tag
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32'b101111?????10000????????????????: valid = 1'b1; // I-Cache Hit Invalid
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32'b101111?????00001????????????????: valid = 1'b1; // D-Cache Index Writeback Invalid
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32'b101111?????01001????????????????: valid = 1'b1; // D-Cache Index Store Tag
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32'b101111?????10001????????????????: valid = 1'b1; // D-Cache Hit Invalid
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32'b101111?????10101????????????????: valid = 1'b1; // D-Cache Hit Writeback Invalid
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32'b110011??????????????????????????: valid = 1'b1; // PREF (NOP)
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// 32'b101111?????00000????????????????: valid = 1'b1; // I-Cache Index Invalid
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// 32'b101111?????01000????????????????: valid = 1'b1; // I-Cache Index Store Tag
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// 32'b101111?????10000????????????????: valid = 1'b1; // I-Cache Hit Invalid
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// 32'b101111?????00001????????????????: valid = 1'b1; // D-Cache Index Writeback Invalid
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// 32'b101111?????01001????????????????: valid = 1'b1; // D-Cache Index Store Tag
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// 32'b101111?????10001????????????????: valid = 1'b1; // D-Cache Hit Invalid
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// 32'b101111?????10101????????????????: valid = 1'b1; // D-Cache Hit Writeback Invalid
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default: valid = 1'b0;
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endcase
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endmodule
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@ -12,8 +12,9 @@ module MMU (
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ICache_i.mmu ic,
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DCache_i.mmu dc,
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sramro_i.slave inst,
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sram_i.slave data,
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sramro_i.slave inst,
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sram_i.slave data,
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input CacheOp_t cacheOp,
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SRAM_RO_AXI_i.master inst_axi,
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SRAM_RO_AXI_i.master rdata_axi,
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@ -309,6 +310,8 @@ module MMU (
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logic dUser1;
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word_t dPA1, dPA2;
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logic [1:0] dSize1;
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CacheOp_t cacheOp1, cacheOp2;
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logic dEn2;
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logic dwr1;
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@ -325,49 +328,15 @@ module MMU (
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// ======== dFlip-Flop ========
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// ============================
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ffenr #(1) dvalid_ff (
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clk,
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rst,
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data.req,
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dEn,
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dReq1
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);
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ffen #(2) dsize_ff (
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clk,
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data.size,
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dEn,
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dSize1
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);
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ffen #(32) dPA_ff (
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clk,
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dPA1,
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dEn2,
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dPA2
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);
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ffen #(1) dCached_ff (
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clk,
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dCached1,
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dEn2,
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dCached2
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);
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ffen #(1) dwr_ff (
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clk,
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data.wr,
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dEn2,
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dwr1
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);
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ffen #(4) dwstrb_ff (
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clk,
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data.wstrb,
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dEn2,
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dWstrb1
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);
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ffen #(32) dwdata_ff (
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clk,
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data.wdata,
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dEn2,
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dWdata1
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);
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ffenr #(1) dvalid_ff (clk, rst, data.req, dEn, dReq1);
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ffen #(2) dsize_ff (clk, data.size, dEn, dSize1);
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ffen #(32) dPA_ff (clk, dPA1, dEn2, dPA2);
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ffen #(1) dCached_ff (clk, dCached1, dEn2, dCached2);
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ffen #(1) dwr_ff (clk, data.wr, dEn2, dwr1);
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ffen #(4) dwstrb_ff (clk, data.wstrb, dEn2, dWstrb1);
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ffen #(32) dwdata_ff (clk, data.wdata, dEn2, dWdata1);
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ffen #(3) cache_op_ff (clk, cacheOp, dEn, cacheOp1);
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ffen #(3) cache_op2_ff (clk, cacheOp1, dEn2, cacheOp2);
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// =================================
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// ======== drState Machine ========
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@ -393,7 +362,7 @@ module MMU (
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else begin
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dEn2 = 1;
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if (data.wr) data.data_ok = 1;
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if (data.wr & (~dCached1 | dc.hit)) drNextState = DR_REFILL;
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if (data.wr & (~dCached1 | dc.hit | cacheOp1[2])) drNextState = DR_REFILL;
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else if (dCached1 & dc.hit) begin
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dEn = 1;
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data.data_ok = 1;
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@ -453,10 +422,10 @@ module MMU (
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assign dVA = data.addr;
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assign dValid1 = dReq1 & dHit1 & dMValid1 & (~data.wr | dDirty1) & (in_kernel | dUser1);
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assign dTLBRefill = (drState == DR_IDLE) & dReq1 & ~dHit1;
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assign dTLBInvalid = (drState == DR_IDLE) & dReq1 & ~dMValid1;
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assign dTLBModified = (drState == DR_IDLE) & dReq1 & data.wr & ~dDirty1;
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assign dAddressError = (drState == DR_IDLE) & dReq1 & ~in_kernel & ~dUser1;
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assign dTLBRefill = (drState == DR_IDLE) & dReq1 & ~cacheOp1[1] & ~dHit1;
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assign dTLBInvalid = (drState == DR_IDLE) & dReq1 & ~cacheOp1[1] & ~dMValid1;
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assign dTLBModified = (drState == DR_IDLE) & dReq1 & ~cacheOp1[1] & data.wr & ~dDirty1;
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assign dAddressError = (drState == DR_IDLE) & dReq1 & ~cacheOp1[1] & ~in_kernel & ~dUser1;
|
||||
|
||||
// =============================
|
||||
// ======== drFlip-Flop ========
|
||||
@ -537,7 +506,11 @@ module MMU (
|
||||
|
||||
case (dwState)
|
||||
DW_IDLE: begin
|
||||
if (dEn2 & (~dCached1 & data.wr | dCached1 & ~dc.hit & dc.dirt_valid)) begin
|
||||
if (dEn2 & (~dCached1 & data.wr
|
||||
| dCached1 & dc.dirt_valid
|
||||
& (~cacheOp1[2] | ~cacheOp1[0]) // WriteOnly 不允许写回
|
||||
& (~dc.hit | cacheOp1[2] & ~cacheOp1[0]) // Writeback Invalid 直接写回
|
||||
)) begin
|
||||
if (dCached1) begin
|
||||
wdata_axi.wdata = dc.dirt_data[31:0];
|
||||
wdata_axi.wstrb = 4'b1111;
|
||||
@ -646,7 +619,11 @@ module MMU (
|
||||
|
||||
case (dwaState)
|
||||
DWA_IDLE: begin
|
||||
if (dEn2 & (~dCached1 & data.wr | dCached1 & ~dc.hit & dc.dirt_valid)) begin
|
||||
if (dEn2 & (~dCached1 & data.wr
|
||||
| dCached1 & dc.dirt_valid
|
||||
& (~cacheOp1[2] | ~cacheOp1[0]) // WriteOnly 不允许写回
|
||||
& (~dc.hit | cacheOp1[2] & ~cacheOp1[0])) // Writeback Invalid 直接写回
|
||||
) begin
|
||||
wdata_axi.req = 1'b1;
|
||||
if (~wdata_axi.addr_ok) dwaNextState = DWA_WA;
|
||||
end
|
||||
@ -685,6 +662,8 @@ module MMU (
|
||||
assign dc.wvalid = dEn2 ? data.wr : dwr1;
|
||||
assign dc.wdata = dEn2 ? data.wdata : dWdata1;
|
||||
assign dc.wstrb = dEn2 ? data.wstrb : dWstrb1;
|
||||
assign dc.clear = dEn2 ? cacheOp1[2] & dCached1 & (dc.hit | cacheOp1[1])
|
||||
: cacheOp2[2] & dCached2;
|
||||
|
||||
// ==============================
|
||||
// ========== VA -> PA ==========
|
||||
|
||||
@ -79,6 +79,8 @@ module mycpu_top (
|
||||
|
||||
sramro_i inst ();
|
||||
sram_i data ();
|
||||
|
||||
CacheOp_t cache_op;
|
||||
|
||||
logic C0_int;
|
||||
logic [4:0] C0_addr;
|
||||
@ -135,6 +137,7 @@ module mycpu_top (
|
||||
.dc (dcache.mmu),
|
||||
.inst (inst.slave),
|
||||
.data (data.slave),
|
||||
.cacheOp (cache_op),
|
||||
.inst_axi (inst_axi.master),
|
||||
.rdata_axi (rdata_axi.master),
|
||||
.wdata_axi (wdata_axi.master),
|
||||
|
||||
@ -2,7 +2,6 @@
|
||||
`define CP0_SVH
|
||||
|
||||
`include "defines.svh"
|
||||
`include "Cache.svh"
|
||||
`include "TLB.svh"
|
||||
|
||||
typedef enum bit [4:0] {
|
||||
@ -94,8 +93,8 @@ typedef struct packed {
|
||||
// ==== sel0 ====
|
||||
// word_t DESAVE,
|
||||
// ErrorEPC,
|
||||
// word_t TagHi;
|
||||
TagLo_t TagLo;
|
||||
// TagHi
|
||||
word_t TagLo;
|
||||
// CacheErr,
|
||||
// Errctl,
|
||||
// PerfCnt,
|
||||
@ -109,7 +108,7 @@ typedef struct packed {
|
||||
// LLAddr
|
||||
// ;
|
||||
CP0_REGS_CONFIG_t Config;
|
||||
word_t PRId;
|
||||
word_t PRId;
|
||||
word_t EPC;
|
||||
CP0_REGS_CAUSE_t Cause;
|
||||
CP0_REGS_STATUS_t Status;
|
||||
|
||||
@ -1,11 +0,0 @@
|
||||
`ifndef CACHE_SVH
|
||||
`define CACHE_SVH
|
||||
|
||||
typedef struct packed {
|
||||
logic [ 8:0] zero;
|
||||
logic [20:0] Tag;
|
||||
logic D;
|
||||
logic V;
|
||||
} TagLo_t;
|
||||
|
||||
`endif
|
||||
@ -49,18 +49,21 @@ interface DCache_i;
|
||||
word_t dirt_addr;
|
||||
DCData_t dirt_data;
|
||||
DCData_t row;
|
||||
logic clear;
|
||||
|
||||
modport cache(
|
||||
input req, valid,
|
||||
input index, tag1, sel1,
|
||||
input rvalid, rdata, wvalid, wdata, wstrb,
|
||||
output hit, dirt_valid, dirt_addr, dirt_data, row
|
||||
input req, valid,
|
||||
input index, tag1, sel1,
|
||||
input rvalid, rdata, wvalid, wdata, wstrb,
|
||||
output hit, dirt_valid, dirt_addr, dirt_data, row,
|
||||
input clear
|
||||
);
|
||||
modport mmu(
|
||||
output req, valid,
|
||||
output index, tag1, sel1,
|
||||
output rvalid, rdata, wvalid, wdata, wstrb,
|
||||
input hit, dirt_valid, dirt_addr, dirt_data, row
|
||||
output req, valid,
|
||||
output index, tag1, sel1,
|
||||
output rvalid, rdata, wvalid, wdata, wstrb,
|
||||
input hit, dirt_valid, dirt_addr, dirt_data, row,
|
||||
output clear
|
||||
);
|
||||
endinterface //DCache_i
|
||||
|
||||
|
||||
@ -41,15 +41,22 @@ interface ICache_i;
|
||||
ICData_t row;
|
||||
logic rvalid;
|
||||
ICData_t rdata;
|
||||
logic clear;
|
||||
|
||||
modport cache(input req, valid,
|
||||
input index, tag1,
|
||||
output hit, row,
|
||||
input rvalid, rdata);
|
||||
modport mmu(output req, valid,
|
||||
output index, tag1,
|
||||
input hit, row,
|
||||
output rvalid, rdata);
|
||||
modport cache(
|
||||
input req, valid,
|
||||
input index, tag1,
|
||||
output hit, row,
|
||||
input rvalid, rdata,
|
||||
input clear
|
||||
);
|
||||
modport mmu(
|
||||
output req, valid,
|
||||
output index, tag1,
|
||||
input hit, row,
|
||||
output rvalid, rdata,
|
||||
output clear
|
||||
);
|
||||
endinterface //ICache_i
|
||||
|
||||
`endif
|
||||
|
||||
@ -83,6 +83,16 @@ typedef enum logic [1:0] {
|
||||
URIGHT = 2'b10
|
||||
} ALR_t;
|
||||
|
||||
typedef enum logic [2:0] {
|
||||
CNOP = 3'b000,
|
||||
IC_L = 3'b001, // I-Cache Lookup
|
||||
IC_I = 3'b011, // I-Cache Index
|
||||
DC_LB = 3'b100, // D-Cache Lookup writeBack
|
||||
DC_LO = 3'b101, // D-Cache Lookup writeOnly
|
||||
DC_IB = 3'b110, // D-Cache Index writeBack
|
||||
DC_IO = 3'b111 // D-Cache Index writeOnly
|
||||
} CacheOp_t;
|
||||
|
||||
typedef struct packed {
|
||||
SA_t SA;
|
||||
SB_t SB;
|
||||
@ -101,15 +111,16 @@ typedef struct packed {
|
||||
} MCtrl0_t;
|
||||
|
||||
typedef struct packed {
|
||||
logic MR; // critical
|
||||
logic MWR; // critical
|
||||
logic MR; // critical
|
||||
logic MWR; // critical
|
||||
logic MX;
|
||||
ALR_t ALR; // critical
|
||||
ALR_t ALR; // critical
|
||||
logic [1:0] SZ;
|
||||
logic TLBWI; // critical
|
||||
logic TLBWR; // critical
|
||||
logic TLBR; // critical
|
||||
logic TLBP; // critical
|
||||
logic TLBWI; // critical
|
||||
logic TLBWR; // critical
|
||||
logic TLBR; // critical
|
||||
logic TLBP; // critical
|
||||
CacheOp_t CACHE_OP; // critical
|
||||
} MCtrl1_t;
|
||||
|
||||
typedef struct packed {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user