refactor CACHE inst on D-CACHE
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@ -1462,8 +1462,10 @@
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LI(t2, data1); \
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LI(t3, data2); \
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/* prepare -> hit writeback invalidate */ \
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sw t2, offset(t0); \
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sw t2, offset(t1); \
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cache 21, offset(t1); \
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lw a0, offset(t0); \
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bne t2, a0, inst_error; \
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lw a0, offset(t1); \
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bne t2, a0, inst_error; \
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nop; \
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@ -1472,12 +1474,16 @@
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cache 17, offset(t1); \
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lw a0, offset(t0); \
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bne a0, t2, inst_error; \
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lw a0, offset(t1); \
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bne a0, t2, inst_error; \
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nop; \
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/* test hit writeback invalidate */ \
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sw t3, offset(t1); \
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cache 21, offset(t1); \
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lw a0, offset(t0); \
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bne a0, t3, inst_error; \
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lw a0, offset(t1); \
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bne a0, t3, inst_error; \
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nop; \
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/* test multiple*/ \
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addi a1, t1, 4; \
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@ -8,6 +8,9 @@ LEAF(n98_cache_dcache_test)
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li s2, 0x0
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###test inst
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## CACHE 17 D-Cache Hit Invalid
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## CACHE 21 D-Cache Hit Writeback Invalid
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TEST_CACHE_DCACHE_HIT(0xa00d0000, 0x800d0000, 0, 0xA5A5A5A5, 0x12345678)
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TEST_CACHE_DCACHE_HIT(0xa00d0004, 0x800d0004, 0, 0xABCDEFAB, 0xF0F0F0F0)
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TEST_CACHE_DCACHE_HIT(0xa00d0008, 0x800d0008, 4, 0x87654321, 0xAABBCCDD)
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@ -125,7 +128,80 @@ TEST_CACHE_DCACHE_HIT(0xa00d0028, 0x800d0028, 4, 0xF0F0F0F0, 0xABCDEFAB)
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nop
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/* TEST D-CACHE Index OP */
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## CACHE 1 D-Cache Index Writeback Invalid
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## CACHE 9 D-Cache Index Store Tag
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.n98_c1_prepare:
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li a0, 0x12345678
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li v0, 0x800d0000
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li v1, 0x800d0200
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.n98_c1_loop:
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beq v0, v1, .n98_c1_check
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sw a0, 0(v0)
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sw a0, 4(v0)
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sw a0, 8(v0)
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sw a0, 12(v0)
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addi a1, v0, 0
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GET_DCACHE_INDEX
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cache 0, 0(v0)
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addi v0, a1, 16
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j .n98_c1_loop
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.n98_c1_check:
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li v0, 0xa00d0000
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li v1, 0xa00d0200
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.n98_c1_check_loop:
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beq v0, v1, .n98_c1_check2
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lw a1, 0(v0)
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bne a0, a1, inst_error
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addi v0, v0, 4
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j .n98_c1_check_loop
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.n98_c1_check2:
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li v0, 0x800d0000
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li v1, 0x800d0200
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.n98_c1_check2_loop:
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beq v0, v1, .n98_c9_prepare
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lw a1, 0(v0)
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bne a0, a1, inst_error
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addi v0, v0, 4
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j .n98_c1_check2_loop
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.n98_c9_prepare:
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li v0, 0x800d0000
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li v1, 0x800d0200
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.n98_c9_loop:
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beq v0, v1, .n98_c9_check
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sw zero, 0(v0)
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sw zero, 4(v0)
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sw zero, 8(v0)
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sw zero, 12(v0)
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addi a1, v0, 0
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GET_DCACHE_INDEX
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cache 9, 0(v0)
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addi v0, a1, 16
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j .n98_c9_loop
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.n98_c9_check:
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li v0, 0xa00d0000
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li v1, 0xa00d0200
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.n98_c9_check_loop:
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beq v0, v1, .n98_c9_check2
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lw a1, 0(v0)
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bne a0, a1, inst_error
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addi v0, v0, 4
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j .n98_c9_check_loop
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.n98_c9_check2:
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li v0, 0x800d0000
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li v1, 0x800d0200
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.n98_c9_check2_loop:
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beq v0, v1, .n98_done
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lw a1, 0(v0)
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bne a0, a1, inst_error
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addi v0, v0, 4
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j .n98_c9_check2_loop
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.n98_done:
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nop
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###detect exception
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bne s2, zero, inst_error
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@ -24,22 +24,22 @@ module DCache (
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// ==============================
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// Four way assoc bram controller:
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DCTagRAM_t TagRAM0, TagRAM1, TagRAM2, TagRAM3;
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DCTagRAM_t TagRAM0, TagRAM1, TagRAM2, TagRAM3;
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DCDataRAM_t DataRAM0, DataRAM1, DataRAM2, DataRAM3;
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logic [3:0] LRU[128];
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logic [3:0] nextLRU;
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logic [3:0] nowLRU;
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DCTag_t tagOut[4];
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DCData_t dataOut[4];
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DCTag_t tagOut[4];
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DCData_t dataOut[4];
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logic [3:0] tagV;
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DCIndexL_t index1;
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logic hit;
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logic hit;
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logic [3:0] hitWay;
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DCData_t cacheLine;
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DCData_t cacheLine;
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logic [3:0] victim;
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logic [3:0] wen;
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@ -56,18 +56,8 @@ module DCache (
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// ======== Flip-Flop ========
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// ===========================
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ffen #(`DC_TAGL-`DC_INDEXL) index_ff (
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clk,
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port.index,
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port.req,
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index1
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);
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ffen #(4) wen_ff (
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clk,
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wen,
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en2,
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wen2
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);
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ffen #(`DC_TAGL-`DC_INDEXL) index_ff (clk, port.index, port.req, index1);
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ffen #(4) wen_ff (clk, wen, en2, wen2);
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// ===============================
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// ======== State Machine ========
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@ -97,7 +87,7 @@ module DCache (
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nextState = IDLE;
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end
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end else begin
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if (hit) begin
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if (hit & ~port.clearWb | port.clear & port.clearIdx) begin
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if (port.wvalid) begin
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bwe1 = 1'b1;
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nextState = IDLE;
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@ -161,20 +151,21 @@ module DCache (
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// ==============================
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// Choose Victim
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assign victim = port.clear ? hitWay
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: tagV[0] == 0 ? 4'b0001
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: tagV[1] == 0 ? 4'b0010
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: tagV[2] == 0 ? 4'b0100
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: tagV[3] == 0 ? 4'b1000
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assign victim = port.clearWb ? hitWay
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: tagV[0] == 0 ? 4'b0001
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: tagV[1] == 0 ? 4'b0010
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: tagV[2] == 0 ? 4'b0100
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: tagV[3] == 0 ? 4'b1000
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: nowLRU[0] == 0 & ~tagOut[0].dirty ? 4'b0001
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: nowLRU[1] == 0 & ~tagOut[1].dirty ? 4'b0010
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: nowLRU[2] == 0 & ~tagOut[2].dirty ? 4'b0100
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: nowLRU[3] == 0 & ~tagOut[3].dirty ? 4'b1000
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: nowLRU[0] == 0 ? 4'b0001
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: nowLRU[1] == 0 ? 4'b0010
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: nowLRU[2] == 0 ? 4'b0100
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: nowLRU[0] == 0 ? 4'b0001
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: nowLRU[1] == 0 ? 4'b0010
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: nowLRU[2] == 0 ? 4'b0100
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: 4'b1000;
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assign wen = hit ? hitWay : victim;
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assign wen = port.clear & port.clearIdx ? 4'b1111
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: hit ? hitWay : victim;
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assign port.dirt_valid = (state == LOOKUP)
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& |{tagV & {tagOut[3].dirty, tagOut[2].dirty, tagOut[1].dirty, tagOut[0].dirty} & victim};
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121
src/MMU/MMU.sv
121
src/MMU/MMU.sv
@ -60,12 +60,12 @@ module MMU (
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I_CACHE, I_CACHE_REFILL
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} istate_t;
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typedef enum bit [2:0] {
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typedef enum bit [3:0] {
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DR_IDLE,
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DR_WA,
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DR_WD1, DR_WD2, DR_WD3, DR_WD4,
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DR_REFILL,
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DR_CACHE
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DR_ICACHE, DR_CACHE, DR_CACHE_REFILL, DR_CACHE_CLEAR, DR_CACHE_REQ
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} drstate_t;
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typedef enum bit [2:0] {
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@ -296,6 +296,9 @@ module MMU (
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word_t ddAddr1;
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logic [127:0] ddData1;
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// D-Cache Clear
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logic dClrValid, dClrRv, dClrReq;
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// ============================
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// ======== dFlip-Flop ========
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// ============================
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@ -329,14 +332,34 @@ module MMU (
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drNextState = drState;
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data.data_ok = 0;
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rdata_axi.req = 0;
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dc.clear = 0;
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dc.clearIdx = 0;
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dc.clearWb = 0;
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dClrValid = 0;
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dClrRv = 0;
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dClrReq = 0;
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case (drState)
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DR_IDLE: begin
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if (diReq) drNextState = DR_CACHE;
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else if (~dValid1) dEn = 1;
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if (diReq) drNextState = DR_ICACHE;
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else if (dReq1 & cacheOp1[2] & dCached1) begin
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if (cacheOp2[0]) begin
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// Do not write back
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// dc.valid = dc.wvalid = 1;
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dClrValid = 1;
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dc.clear = 1;
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dc.clearIdx = cacheOp2[1];
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drNextState = DR_CACHE_REFILL;
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end else begin
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// WriteBack
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dc.clearWb = 1;
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drNextState = DR_CACHE;
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dEn2 = 1;
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end
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end else if (~dValid1) dEn = 1;
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else begin
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dEn2 = 1;
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if (data.wr) data.data_ok = 1;
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if (data.wr & (~dCached1 | dc.hit | cacheOp1[2])) drNextState = DR_REFILL;
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if (data.wr & (~dCached1 | dc.hit)) drNextState = DR_REFILL;
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else if (dCached1 & dc.hit) begin
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dEn = 1;
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data.data_ok = 1;
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@ -386,7 +409,7 @@ module MMU (
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drNextState = DR_IDLE;
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end
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end
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DR_CACHE: begin
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DR_ICACHE: begin
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/*
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* 该状态是 I-CACHE 的清除指令
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* 当 iState == I_CACHE_REFILL 代表下一个周期恢复正常工作
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@ -397,6 +420,38 @@ module MMU (
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drNextState = DR_IDLE;
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end
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end
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DR_CACHE: begin
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// WriteBack
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// Clear By Index or Address
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// D-Cache: state == REPLACE
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if (wdata_ok) begin
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if (cacheOp2[1]) begin
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drNextState = DR_CACHE_CLEAR;
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end else begin
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dClrRv = 1;
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dc.clear = 1;
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drNextState = DR_CACHE_REFILL;
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end
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// drNextState = DR_CACHE_CLEAR;
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end
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end
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DR_CACHE_REFILL: begin
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// avoid deadlock
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dEn = 1;
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drNextState = DR_IDLE;
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data.data_ok = 1;
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end
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DR_CACHE_CLEAR: begin
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// deal with timing loop
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dClrRv = 1;
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dc.clear = 1;
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drNextState = DR_CACHE_REQ;
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end
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DR_CACHE_REQ: begin
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// deal with timing loop
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dClrReq = 1; // use dClrReq to start a new D-Cache req
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drNextState = DR_IDLE;
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end
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endcase
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end
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@ -409,16 +464,30 @@ module MMU (
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* Cache 指令当成写指令处理
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* TLB 转换请求和 D-Cache 请求与普通访存一致
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* dc.req 在 I-Cache Cache 指令发生时为0
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* 清除请求时 drState 进入 DR_REFILL 状态，后由 DW_STATE 确定返回
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* dwState 和 dwaState 需判断是否是 CACHE 指令且是否允许写回
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* 屏蔽 dAddressError 和 TLBModified 且只有在 Address 类型请求下允许 TLBRefill 和 TLBInvalid
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* dc.clear 在查询完成后一阶段或者写回完成阶段发送
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* Index WriteBack 转换成 Hit WriteBack(s) + Index Invalid
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*/
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/* 状态
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D-Cache:
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IDLE <- dc.req + dc.index
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LOOKUP <- dc.tag1: Lookup模式下需要传入正确的tag1
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dc.valid: 1
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dc.wvalid: 1
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dc.clear: Hit Invalid and Index Invalid
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dc.clearIdx: Hit Invalid or Index Invalid
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dc.clearWb: 是否需要写回
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-> dc.dirt_valid
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dc.dirt_addr
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dc.dirt_data
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REPLACE <- dc.rvalid
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dc.clear: same cycle as dc.rvalid
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*/
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assign dVA = data.addr;
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assign diReq = dReq1 & ~cacheOp1[2] & |cacheOp1[1:0];
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assign dcReq1 = dReq1 & (cacheOp1 == CNOP | cacheOp1[2]); // exclude I-Cache clear
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assign dValid1 = dReq1 & dHit1 & dMValid1 & (~data.wr | dDirty1) & (in_kernel | dUser1);
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assign dVA = data.addr;
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assign diReq = dReq1 & ~cacheOp1[2] & |cacheOp1[1:0];
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assign dcReq1 = dReq1 & (cacheOp1 == CNOP | cacheOp1[2]); // exclude I-Cache clear
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assign dValid1 = dReq1 & dHit1 & dMValid1 & (~data.wr | dDirty1) & (in_kernel | dUser1);
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assign dTLBRefill = drState == DR_IDLE & dcReq1 & (cacheOp1 == CNOP | ~cacheOp1[1]) & ~dHit1;
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assign dTLBInvalid = drState == DR_IDLE & dcReq1 & (cacheOp1 == CNOP | ~cacheOp1[1]) & ~dMValid1;
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@ -464,12 +533,12 @@ module MMU (
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);
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// do not request when handling CACHE instruction on I-Cache
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assign dc.req = dEn & (cacheOp[2] | ~|cacheOp[1:0]);
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assign dc.valid = dValid1 & (dCached1 & (~cacheOp1[2] | dc.hit) | cacheOp1[1]);
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assign dc.index = dVA[`DC_TAGL-1:`DC_INDEXL];
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assign dc.tag1 = dEn2 ? dPA1[31:`DC_TAGL] : dPA2[31:`DC_TAGL];
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assign dc.sel1 = dEn2 ? dPA1[3:2] : dPA2[3:2];
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assign dc.rvalid = rdata_axi.rvalid & rdata_axi.data_ok;
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assign dc.req = dClrReq | dEn & (cacheOp[2] | ~|cacheOp[1:0]);
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assign dc.valid = dClrValid | dValid1 & dCached1;
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assign dc.index = dEn ? dVA[`DC_TAGL-1:`DC_INDEXL] : dVA1[`DC_TAGL-1:`DC_INDEXL];
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assign dc.tag1 = dEn2 ? dPA1[31:`DC_TAGL] : dPA2[31:`DC_TAGL];
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assign dc.sel1 = dEn2 ? dPA1[3:2] : dPA2[3:2];
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assign dc.rvalid = dClrRv | rdata_axi.rvalid & rdata_axi.data_ok;
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mux4 #(128) dc_rdata_mux (
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{rdata_axi.rdata, drD3, drD2, drD1},
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{drD3, drD2, drD1, rdata_axi.rdata},
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@ -508,7 +577,7 @@ module MMU (
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if (dEn2 & (~dCached1 & data.wr
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| dCached1 & dc.dirt_valid
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& (~cacheOp1[2] | ~cacheOp1[0]) // WriteOnly 不允许写回
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& (~dc.hit | cacheOp1[2] & ~cacheOp1[0]) // Writeback Invalid 直接写回
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& (~dc.hit | cacheOp1[2] & ~cacheOp1[0]) // Writeback 或一般情况
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)) begin
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if (dCached1) begin
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wdata_axi.wdata = dc.dirt_data[31:0];
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@ -583,7 +652,7 @@ module MMU (
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if (~wdata_axi.data_ok) dwNextState = DW_WB;
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else begin
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// fixme: AXI3 wait WA
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if (drState == DR_REFILL) dwNextState = DW_IDLE;
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if (drState == DR_REFILL | drState == DR_CACHE_REFILL) dwNextState = DW_IDLE;
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else dwNextState = DW_WAITR;
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end
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end
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@ -592,12 +661,12 @@ module MMU (
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// TODO: goto IDLE on failure
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if (wdata_axi.data_ok) begin
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// fixme: AXI3 wait WA
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if (drState == DR_REFILL) dwNextState = DW_IDLE;
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if (drState == DR_REFILL | drState == DR_CACHE_REFILL) dwNextState = DW_IDLE;
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else dwNextState = DW_WAITR;
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end
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end
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DW_WAITR: begin
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if (drState == DR_REFILL) dwNextState = DW_IDLE;
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if (drState == DR_REFILL | drState == DR_CACHE_REFILL) dwNextState = DW_IDLE;
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end
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endcase
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end
|
||||
@ -621,8 +690,8 @@ module MMU (
|
||||
if (dEn2 & (~dCached1 & data.wr
|
||||
| dCached1 & dc.dirt_valid
|
||||
& (~cacheOp1[2] | ~cacheOp1[0]) // WriteOnly 不允许写回
|
||||
& (~dc.hit | cacheOp1[2] & ~cacheOp1[0])) // Writeback Invalid 直接写回
|
||||
) begin
|
||||
& (~dc.hit | cacheOp1[2] & ~cacheOp1[0]) // Writeback 或一般情况
|
||||
)) begin
|
||||
wdata_axi.req = 1'b1;
|
||||
if (~wdata_axi.addr_ok) dwaNextState = DWA_WA;
|
||||
end
|
||||
@ -658,11 +727,9 @@ module MMU (
|
||||
assign wdata_axi.addr = (dEn2 ? dCached1 : dCached2) ? (dwaState == DWA_IDLE) ? dc.dirt_addr : ddAddr1 : dEn2 ? dPA1 : dPA2;
|
||||
assign wdata_axi.len = (dEn2 ? dCached1 : dCached2) ? 4'b0011 : 4'b0000;
|
||||
assign wdata_axi.size = (dEn2 ? dCached1 : dCached2) ? 3'b010 : {1'b0, dSize1};
|
||||
assign dc.wvalid = dEn2 ? data.wr : dwr1;
|
||||
assign dc.wvalid = dClrValid | dEn2 ? data.wr : dwr1;
|
||||
assign dc.wdata = dEn2 ? data.wdata : dWdata1;
|
||||
assign dc.wstrb = dEn2 ? data.wstrb : dWstrb1;
|
||||
assign dc.clear = dEn2 ? cacheOp1[2] & dCached1 & (dc.hit | cacheOp1[1])
|
||||
: cacheOp2[2] & dCached2;
|
||||
|
||||
// ==============================
|
||||
// ========== VA -> PA ==========
|
||||
|
||||
@ -50,20 +50,22 @@ interface DCache_i;
|
||||
DCData_t dirt_data;
|
||||
DCData_t row;
|
||||
logic clear;
|
||||
logic clearIdx;
|
||||
logic clearWb;
|
||||
|
||||
modport cache(
|
||||
input req, valid,
|
||||
input index, tag1, sel1,
|
||||
input rvalid, rdata, wvalid, wdata, wstrb,
|
||||
output hit, dirt_valid, dirt_addr, dirt_data, row,
|
||||
input clear
|
||||
input clear, clearIdx, clearWb
|
||||
);
|
||||
modport mmu(
|
||||
output req, valid,
|
||||
output index, tag1, sel1,
|
||||
output rvalid, rdata, wvalid, wdata, wstrb,
|
||||
input hit, dirt_valid, dirt_addr, dirt_data, row,
|
||||
output clear
|
||||
output clear, clearIdx, clearWb
|
||||
);
|
||||
endinterface //DCache_i
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user