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Minimize CP0 when TLB is disabled

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This commit is contained in:
Paul Pan 2022-08-04 16:43:29 +08:00
parent baa2bb049f
commit dfa2e628a2
4 changed files with 41 additions and 20 deletions
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42
src/CP0/CP0.sv
View File

@ -44,6 +44,7 @@ module CP0 (
assign rf_cp0.Status.zero2 = 6'b0;
assign rf_cp0.Status.zero3 = 3'b0;
assign rf_cp0.Status.zero4 = 2'b0;
`ifdef ENABLE_TLB
assign rf_cp0.EntryHi.zero = 5'b0;
assign rf_cp0.Wired.zero = 29'b0;
assign rf_cp0.Context.zero = 4'b0;
@ -51,18 +52,7 @@ module CP0 (
assign rf_cp0.EntryLo0.zero = 6'b0;
assign rf_cp0.Random.zero = 29'b0;
assign rf_cp0.Index.zero = 28'b0;
// Vol III Figure 9-1
// | 31 | 30...25 | 24...22 | 21...19 | 18...16 |
// | Config2 | MMU SIZE | iCache sets per way | iCache line size | iCache associativity |
// | 15...13 | 12...10 | 9...7 |
// | dCache sets per way | dCache line size | dCache associativity |
// | 6 | 5 | 4 |
// | Coprocessor 2 implemented | MD | Performance Counter registers |
// | 3 | 2 |
// | Watch registers implemented | Code compression implemented |
// | 1 | 0 |
// | EJTAG implemented | FPU implemented |
`endif
/*verilator lint_off WIDTH*/
assign rf_cp0.Config1.Config2 = 1'b0;
@ -104,10 +94,13 @@ module CP0 (
rf_cp0.Status.EXL = 1'b0;
rf_cp0.Status.IE = 1'b0;
rf_cp0.Compare = 32'h0;
`ifdef ENABLE_TLB
rf_cp0.EntryHi.VPN2 = 19'b0;
rf_cp0.EntryHi.ASID = 8'b0;
`endif
rf_cp0.Count = 32'h0;
rf_cp0.BadVAddr = 32'h0;
`ifdef ENABLE_TLB
rf_cp0.Wired.Wired = 3'b0;
rf_cp0.Context.PTEBase = 9'b0;
rf_cp0.Context.BadVPN2 = 19'b0;
@ -124,6 +117,7 @@ module CP0 (
rf_cp0.Index.P = 1'b0;
rf_cp0.Index.Index = 3'b0;
rf_cp0.Random.Random = 3'b111;
`endif
rf_cp0.EBase.EBase = 18'b0;
@ -133,8 +127,11 @@ module CP0 (
count_lo = ~count_lo;
if (count_lo == 1) rf_cp0.Count = rf_cp0.Count + 1;
`ifdef ENABLE_TLB
rf_cp0.Random.Random = &rf_cp0.Random.Random ? rf_cp0.Wired.Wired
: rf_cp0.Random.Random + 1'b1;
`endif
if (en) begin
case (addr)
// 31: rf_cp0.DESAVE = wdata;
@ -169,13 +166,16 @@ module CP0 (
rf_cp0.Cause.TI = 0;
rf_cp0.Compare = wdata;
end
`ifdef ENABLE_TLB
10: begin
rf_cp0.EntryHi.VPN2 = wdata[31:13];
rf_cp0.EntryHi.ASID = wdata[7:0];
end
`endif
9: rf_cp0.Count = wdata;
8: rf_cp0.BadVAddr = wdata;
// 7: rf_cp0.HWREna = wdata;
`ifdef ENABLE_TLB
6: begin
rf_cp0.Wired.Wired = wdata[2:0];
rf_cp0.Random.Random = 3'b111;
@ -202,11 +202,13 @@ module CP0 (
0: begin
rf_cp0.Index.Index = wdata[2:0];
end
`endif
default: begin
end
endcase
end
`ifdef ENABLE_TLB
if (c0.cpu_tlbr) begin
rf_cp0.EntryHi.VPN2 = c0.tlb_EntryHi.VPN2;
rf_cp0.EntryHi.ASID = c0.tlb_EntryHi.ASID;
@ -227,6 +229,7 @@ module CP0 (
rf_cp0.Index.P = c0.tlb_Index.P;
rf_cp0.Index.Index = c0.tlb_Index.Index;
end
`endif
if (rf_cp0.Count == rf_cp0.Compare) rf_cp0.Cause.TI = 1;
@ -247,12 +250,14 @@ module CP0 (
rf_cp0.BadVAddr = c0.cpu_exception.BadVAddr;
end
`ifdef ENABLE_TLB
if ( c0.cpu_exception.ExcCode == `EXCCODE_MOD
| c0.cpu_exception.ExcCode == `EXCCODE_TLBL
| c0.cpu_exception.ExcCode == `EXCCODE_TLBS) begin
rf_cp0.Context.BadVPN2 = c0.cpu_exception.BadVAddr[31:13];
rf_cp0.EntryHi.VPN2 = c0.cpu_exception.BadVAddr[31:13];
end
`endif
end
end
@ -282,10 +287,13 @@ module CP0 (
13: rdata = rf_cp0.Cause;
12: rdata = rf_cp0.Status;
11: rdata = rf_cp0.Compare;
`ifdef ENABLE_TLB
10: rdata = rf_cp0.EntryHi;
`endif
9: rdata = rf_cp0.Count;
8: rdata = rf_cp0.BadVAddr;
// 7: rdata = rf_cp0.HWREna;
`ifdef ENABLE_TLB
6: rdata = rf_cp0.Wired;
// 5: rdata = rf_cp0.PageMask;
5: rdata = 32'h0;
@ -294,6 +302,7 @@ module CP0 (
2: rdata = rf_cp0.EntryLo0;
1: rdata = rf_cp0.Random;
0: rdata = rf_cp0.Index;
`endif
default: rdata = 32'h0;
endcase
@ -303,12 +312,19 @@ module CP0 (
assign c0.cp0_K0 = rf_cp0.Config.K0;
assign c0.cp0_CU = rf_cp0.Status.CU;
`ifdef ENABLE_TLB
assign c0.cp0_Random = rf_cp0.Random;
assign c0.cp0_Index = rf_cp0.Index;
assign c0.cp0_EntryHi = rf_cp0.EntryHi;
// assign PageMask = rf_cp0.PageMask;
assign c0.cp0_EntryLo1 = rf_cp0.EntryLo1;
assign c0.cp0_EntryLo0 = rf_cp0.EntryLo0;
`else
assign c0.cp0_Random = 0;
assign c0.cp0_Index = 0;
assign c0.cp0_EntryHi = 0;
assign c0.cp0_EntryLo1 = 0;
assign c0.cp0_EntryLo0 = 0;
`endif
assign c0.cp0_in_kernel = ~rf_cp0.Status.UM | rf_cp0.Status.EXL; // currently no ERL

6
src/include/CP0.svh
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@ -134,17 +134,19 @@ typedef struct packed {
CP0_REGS_CAUSE_t Cause;
CP0_REGS_STATUS_t Status;
word_t Compare;
`ifdef ENABLE_TLB
EntryHi_t EntryHi;
`endif
word_t Count;
word_t BadVAddr;
// HWREna
`ifdef ENABLE_TLB
Wired_t Wired;
Context_t Context;
// word_t PageMask;
EntryLo_t EntryLo1;
EntryLo_t EntryLo0;
Random_t Random;
Index_t Index;
`endif
// ==== sel1 ====
CP0_REGS_CONFIG1_t Config1;

3
src/include/Cache.svh
View File

@ -3,6 +3,9 @@
`include "defines.svh"
// TAGL <= 12
// INDEXL <= 6
// IC for I-Cache
`define IC_TAGL 12
`define IC_INDEXL 6

10
src/include/defines.svh
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@ -3,11 +3,11 @@
// `define ILA_DEBUG
`define ENABLE_CACHEOP
`define ENABLE_TLB
`define ENABLE_CpU
`define ENABLE_TRAP
`define ENABLE_MADD
// `define ENABLE_CACHEOP
// `define ENABLE_TLB
// `define ENABLE_CpU
// `define ENABLE_TRAP
// `define ENABLE_MADD
`ifdef SIMULATION_VERILATOR
`undef ENABLE_CpU