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update Controller and Datapath

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This commit is contained in:
Paul Pan 2021-09-02 11:05:33 +08:00
parent 3dffdae575
commit ed49e734d8
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GPG Key ID: DA97C6DCB84DEC68
3 changed files with 34 additions and 31 deletions
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21
src/Core/Controller.sv
View File

@ -24,7 +24,7 @@ module Controller (
{16'b0, inst[15:0]},
{{16{inst[15]}}, inst[15:0]},
{inst[15:0], 16'b0},
{inst[28] & inst[27] & inst[26], inst[31] | ~inst[28]},
{~inst[31] & inst[28] & inst[27] & inst[26], inst[31] | ~inst[28]},
imm
);
@ -70,15 +70,16 @@ module Controller (
assign ctrl.MCtrl0.SEL = inst[2:0];
assign ctrl.MCtrl0.RS0 = RS0_t'({~inst[30] & (inst[29] | inst[26] | ~inst[4]), inst[30], ~inst[29] & (inst[30] | ~inst[1])});
assign ctrl.MCtrl1.MR = inst[31] & ~inst[30];
assign ctrl.MCtrl1.MWR = inst[29];
assign ctrl.MCtrl1.MX = ~inst[28];
assign ctrl.MCtrl1.ALR = ALR_t'({inst[28] & inst[27], ~inst[28] & inst[27] & ~inst[26]});
assign ctrl.MCtrl1.SZ = inst[27:26];
assign ctrl.MCtrl1.TLBR = ~inst[31] & inst[30] & ~inst[29] & inst[25] & ~inst[3] & ~inst[1];
assign ctrl.MCtrl1.TLBWI = ~inst[31] & inst[30] & ~inst[29] & inst[25] & ~inst[3] & inst[1];
assign ctrl.MCtrl1.TLBWR = ~inst[31] & inst[30] & ~inst[29] & inst[25] & ~inst[3] & (inst[2] | ~inst[1]);
assign ctrl.MCtrl1.TLBP = ~inst[31] & inst[30] & ~inst[4] & inst[3];
assign ctrl.MCtrl1.MR = inst[31] & ~inst[30];
assign ctrl.MCtrl1.MWR = inst[29];
assign ctrl.MCtrl1.MX = ~inst[28];
assign ctrl.MCtrl1.ALR = ALR_t'({inst[28] & inst[27] & ~inst[26], inst[27] & ~inst[26]});
assign ctrl.MCtrl1.SZ = inst[27:26];
assign ctrl.MCtrl1.TLBR = ~inst[31] & inst[30] & ~inst[29] & inst[25] & ~inst[3] & ~inst[1];
assign ctrl.MCtrl1.TLBWI = ~inst[31] & inst[30] & ~inst[29] & inst[25] & ~inst[3] & inst[1];
assign ctrl.MCtrl1.TLBWR = ~inst[31] & inst[30] & ~inst[29] & inst[25] & ~inst[3] & (inst[2] | ~inst[1]);
assign ctrl.MCtrl1.TLBP = ~inst[31] & inst[30] & ~inst[4] & inst[3];
assign ctrl.MCtrl1.CACHE_OP = CacheOp_t'({inst[29] & inst[28] & inst[26] & inst[16], inst[29] & inst[28] & inst[26] & ~inst[20], inst[29] & inst[28] & inst[26] & ~inst[18] & (inst[20] | inst[19] | ~inst[16])});
assign ctrl.WCtrl.RW = ctrl.RD != 5'b00000 & (~inst[30] & (~inst[27] & (~inst[26] & (~inst[31] & (~inst[28] & (~inst[3] & (~inst[4] | ~inst[0]) | inst[3] & (~inst[4] & ~inst[2] & inst[0] | inst[5])) | inst[29]) | inst[31] & ~inst[29]) | inst[26] & (~inst[31] & (~inst[28] & inst[20] | inst[29]) | inst[31] & ~inst[29])) | inst[27] & (~inst[26] & (~inst[31] & inst[29] | inst[31] & ~inst[29]) | inst[26] & (~inst[31] & (~inst[28] | inst[29]) | inst[31] & ~inst[29]))) | inst[30] & ~inst[31] & ~inst[3] & (~inst[29] & ~inst[25] & ~inst[23] | inst[29] & inst[1]));

35
src/Core/Datapath.sv
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@ -7,20 +7,21 @@ module Datapath (
input rst,
// MMU
sramro_i.master fetch_i,
sram_i.master mem_i,
input logic iTLBRefill,
input logic iTLBInvalid,
input logic iAddressError,
input logic dTLBRefill,
input logic dTLBInvalid,
input logic dTLBModified,
input logic dAddressError,
output logic tlb_tlbwi,
output logic tlb_tlbwr,
output logic tlb_tlbp,
output logic c0_tlbr,
output logic c0_tlbp,
sramro_i.master fetch_i,
sram_i.master mem_i,
output CacheOp_t cache_op,
input logic iTLBRefill,
input logic iTLBInvalid,
input logic iAddressError,
input logic dTLBRefill,
input logic dTLBInvalid,
input logic dTLBModified,
input logic dAddressError,
output logic tlb_tlbwi,
output logic tlb_tlbwr,
output logic tlb_tlbp,
output logic c0_tlbr,
output logic c0_tlbp,
// CP0
input logic C0_int,
@ -780,7 +781,7 @@ module Datapath (
E.en,
E.I1.ECtrl
);
ffenrc #(11) E_I1_MCtrl_ff (
ffenrc #(14) E_I1_MCtrl_ff (
clk,
rst | rstM,
D.I1.MCtrl,
@ -917,7 +918,7 @@ module Datapath (
assign E_I1_ADDR = E_I1_ForwardS + E.I1.imm;
assign mem_i.addr = |E.I1.MCtrl.ALR ? {E_I1_ADDR[31:2], 2'b0} : E_I1_ADDR;
assign mem_i.size = {E.I1.MCtrl.SZ[1], E.I1.MCtrl.SZ[0] & ~E.I1.MCtrl.SZ[1]};
// assign mem_i.addr = E.I1.ALUOut;
assign cache_op = E.I1.MCtrl.CACHE_OP;
assign E.en = E_go & M.en;
assign E_go = ~mem_i.req | mem_i.addr_ok;
@ -1069,7 +1070,7 @@ module Datapath (
M.en,
M.I1.ALUOut
);
ffenrc #(11) M_I1_MCtrl_ff (
ffenrc #(14) M_I1_MCtrl_ff (
clk,
rst | rstM,
E.I1.MCtrl,

9
src/MyCPU.sv
View File

@ -210,10 +210,11 @@ module mycpu_top (
);
Datapath datapath (
.clk (aclk),
.rst (~aresetn),
.fetch_i(inst.master),
.mem_i (data.master),
.clk (aclk),
.rst (~aresetn),
.fetch_i (inst.master),
.mem_i (data.master),
.cache_op(cache_op),
.iTLBRefill (iTLBRefill),
.iTLBInvalid (iTLBInvalid),