feat: reconfigure crossbar
This commit is contained in:
parent
7b33e4213a
commit
bf7ee46645
@ -92,34 +92,34 @@ module axi_crossbar #
|
||||
parameter M_SECURE = {M_COUNT{1'b0}},
|
||||
// Slave interface AW channel register type (input)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter S_AW_REG_TYPE = {S_COUNT{2'd0}},
|
||||
parameter S_AW_REG_TYPE = {S_COUNT{2'd1}},
|
||||
// Slave interface W channel register type (input)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter S_W_REG_TYPE = {S_COUNT{2'd0}},
|
||||
parameter S_W_REG_TYPE = {S_COUNT{2'd1}},
|
||||
// Slave interface B channel register type (output)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter S_B_REG_TYPE = {S_COUNT{2'd0}},
|
||||
parameter S_B_REG_TYPE = {S_COUNT{2'd1}},
|
||||
// Slave interface AR channel register type (input)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter S_AR_REG_TYPE = {S_COUNT{2'd0}},
|
||||
parameter S_AR_REG_TYPE = {S_COUNT{2'd1}},
|
||||
// Slave interface R channel register type (output)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter S_R_REG_TYPE = {S_COUNT{2'd0}},
|
||||
parameter S_R_REG_TYPE = {S_COUNT{2'd1}},
|
||||
// Master interface AW channel register type (output)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter M_AW_REG_TYPE = {M_COUNT{2'd0}},
|
||||
parameter M_AW_REG_TYPE = {M_COUNT{2'd1}},
|
||||
// Master interface W channel register type (output)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter M_W_REG_TYPE = {M_COUNT{2'd0}},
|
||||
parameter M_W_REG_TYPE = {M_COUNT{2'd1}},
|
||||
// Master interface B channel register type (input)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter M_B_REG_TYPE = {M_COUNT{2'd0}},
|
||||
parameter M_B_REG_TYPE = {M_COUNT{2'd1}},
|
||||
// Master interface AR channel register type (output)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter M_AR_REG_TYPE = {M_COUNT{2'd0}},
|
||||
parameter M_AR_REG_TYPE = {M_COUNT{2'd1}},
|
||||
// Master interface R channel register type (input)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter M_R_REG_TYPE = {M_COUNT{2'd0}}
|
||||
parameter M_R_REG_TYPE = {M_COUNT{2'd1}}
|
||||
)
|
||||
(
|
||||
input wire clk,
|
||||
|
@ -14,7 +14,7 @@ int main(int argc, char **argv, char **env) {
|
||||
Verilated::mkdir("logs");
|
||||
|
||||
const int reset_time = 10;
|
||||
const int time_limit = 20000;
|
||||
const int time_limit = 2000000;
|
||||
|
||||
Vtestbench_top *top = new Vtestbench_top;
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user