Go to file
Paul Pan 7b33e4213a a big update
1. add test soft
2. modify verilator (TODO: crossbar need to replace)
3. fix CP0: now CU0 is always 1
4. Controller: cacheop
5. Controller: fix TEN
6. mycpu_top fix CP0_i
7. fix AXI.sv
8. fix AXIReader.sv
9. fix AXIWriter.sv: getting the correct data and length
10. MU: fix cache writeback, fix mem data mux, fix writer address, fix read request
2022-07-29 18:25:58 +08:00
resources a big update 2022-07-29 18:25:58 +08:00
sim a big update 2022-07-29 18:25:58 +08:00
src a big update 2022-07-29 18:25:58 +08:00
tools a big update 2022-07-29 18:25:58 +08:00
.editorconfig feat: MU rewrite 1 2022-07-27 15:07:16 +08:00
.gitignore feat: MU rewrite 1 2022-07-27 15:07:16 +08:00
README.md clean up 2021-10-14 22:31:25 +08:00

Magically Improved Pipeline Stages

Our awesome MIPS CPU written in SystemVerilog for Loongson Cup 2021

.
├── resources                <-- 资源
│   ├── 2021                 <-- 2021 资源包
│   ├── ping-pong-mips32     <-- 决赛项目 ping pong
│   └── system_top           <-- 决赛项目 ping pong 用的外围顶层
├── src                      <-- CPU设计代码
│   ├── AXI                  <-- AXI总线交互
│   ├── Cache                <-- Cache
│   ├── Core                 <-- CPU核心
│   ├── CP0                  <-- CP0 协处理器
│   ├── Gadgets              <-- 小部件
│   ├── include              <-- 头文件
│   ├── IP                   <-- 用到的IP
│   └── MMU                  <-- 地址转换单元
└── tools                    <-- 控制信号生成器