refactor D-Cache CACHE inst
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@ -32,8 +32,8 @@ Our awesome `MIPS` CPU written in `SystemVerilog` for Loongson Cup
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| :----------------: | :-------------------------------: | :------: | :--: | :-------------------------------------- |
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| :heavy_check_mark: | `I-Cache Index Invalid` | `SYS` | 2 | |
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| :heavy_check_mark: | `I-Cache Hit Invalid` | `SYS` | 2 | |
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| :hourglass: | `D-Cache Index Writeback Invalid` | `SYS` | 2 | :cry: |
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| :hourglass: | `D-Cache Index Store Tag` | `SYS` | 2 | |
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| :heavy_check_mark: | `D-Cache Index Writeback Invalid` | `SYS` | 2 | :cry: |
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| :heavy_check_mark: | `D-Cache Index Store Tag` | `SYS` | 2 | |
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| :heavy_check_mark: | `D-Cache Hit Invalid` | `SYS` | 2 | |
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| :heavy_check_mark: | `D-Cache Hit Writeback Invalid` | `SYS` | 2 | |
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| :heavy_check_mark: | `PREF` | `SYS` | 1 | Treat as `NOP` |
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@ -92,6 +92,7 @@ TEST_CACHE_DCACHE_HIT(0xa00d0028, 0x800d0028, 4, 0xF0F0F0F0, 0xABCDEFAB)
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add v1, v0, v1
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.n98_con_prepare3_loop:
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beq v0, v1, .n98_con_check3
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nop
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sw a0, 0(v0)
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sw a0, 4(v0)
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sw a0, 8(v0)
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@ -110,6 +111,7 @@ TEST_CACHE_DCACHE_HIT(0xa00d0028, 0x800d0028, 4, 0xF0F0F0F0, 0xABCDEFAB)
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add v1, v0, v1
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.n98_con_check4_loop:
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beq v0, v1, .n98_con_end
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nop
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lw a1, 0(v0)
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bne a0, a1, inst_error
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nop
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@ -134,18 +136,19 @@ TEST_CACHE_DCACHE_HIT(0xa00d0028, 0x800d0028, 4, 0xF0F0F0F0, 0xABCDEFAB)
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## CACHE 9 D-Cache Index Store Tag
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.n98_c1_prepare:
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li a0, 0x12345678
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li a0, 0x11223344
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li v0, 0x800d0000
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li v1, 0x800d0200
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.n98_c1_loop:
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beq v0, v1, .n98_c1_check
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nop
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sw a0, 0(v0)
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sw a0, 4(v0)
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sw a0, 8(v0)
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sw a0, 12(v0)
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addi a1, v0, 0
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GET_DCACHE_INDEX
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cache 0, 0(v0)
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cache 1, 0(v0)
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addi v0, a1, 16
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j .n98_c1_loop
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nop
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@ -180,6 +183,7 @@ TEST_CACHE_DCACHE_HIT(0xa00d0028, 0x800d0028, 4, 0xF0F0F0F0, 0xABCDEFAB)
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li v1, 0x800d0200
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.n98_c9_loop:
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beq v0, v1, .n98_c9_check
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nop
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sw zero, 0(v0)
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sw zero, 4(v0)
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sw zero, 8(v0)
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@ -195,6 +199,7 @@ TEST_CACHE_DCACHE_HIT(0xa00d0028, 0x800d0028, 4, 0xF0F0F0F0, 0xABCDEFAB)
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li v1, 0xa00d0200
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.n98_c9_check_loop:
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beq v0, v1, .n98_c9_check2
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nop
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lw a1, 0(v0)
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bne a0, a1, inst_error
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nop
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@ -206,6 +211,7 @@ TEST_CACHE_DCACHE_HIT(0xa00d0028, 0x800d0028, 4, 0xF0F0F0F0, 0xABCDEFAB)
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li v1, 0x800d0200
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.n98_c9_check2_loop:
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beq v0, v1, .n98_done
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nop
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lw a1, 0(v0)
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bne a0, a1, inst_error
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nop
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@ -52,12 +52,15 @@ module DCache (
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DCData_t wdata1[4], wdata2[4];
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logic clear;
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// ===========================
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// ======== Flip-Flop ========
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// ===========================
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ffen #(`DC_TAGL-`DC_INDEXL) index_ff (clk, port.index, port.req, index1);
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ffen #(4) wen_ff (clk, wen, en2, wen2);
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ffen #(`DC_TAGL-`DC_INDEXL) index_ff (clk, port.index, port.req, index1);
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ffen #(4) wen_ff (clk, wen, en2, wen2);
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ffen #(1) clear_ff (clk, port.clearWb, en2, clear);
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// ===============================
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// ======== State Machine ========
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@ -82,12 +85,12 @@ module DCache (
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end
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end
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LOOKUP: begin
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if (~port.valid) begin
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if (~port.valid & ~port.clearWb) begin
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if (~port.req) begin
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nextState = IDLE;
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end
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end else begin
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if (hit & ~port.clearWb | port.clear & port.clearIdx) begin
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if (hit & ~port.clearWb | port.clear & ~port.clearWb) begin
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if (port.wvalid) begin
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bwe1 = 1'b1;
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nextState = IDLE;
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@ -136,7 +139,8 @@ module DCache (
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assign hitWay[1] = tagV[1] & tagOut[1].tag == port.tag1;
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assign hitWay[2] = tagV[2] & tagOut[2].tag == port.tag1;
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assign hitWay[3] = tagV[3] & tagOut[3].tag == port.tag1;
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assign hit = |{hitWay};
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// 在 clearWb状态下确保命中
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assign hit = |{hitWay} | port.clear & port.clearWb;
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assign cacheLine = (hitWay[0] ? dataOut[0] : `DC_DATA_LENGTH'b0)
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| (hitWay[1] ? dataOut[1] : `DC_DATA_LENGTH'b0)
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@ -151,7 +155,13 @@ module DCache (
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// ==============================
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// Choose Victim
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assign victim = port.clearWb ? hitWay
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assign victim = port.clear & port.clearWb & ~port.clearIdx ? hitWay // Hit Address Writeback -> hitWay
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// Hit Index Writeback -> clear valid + dirty way
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: port.clear & port.clearWb & port.clearIdx & tagV[0] & tagOut[0].dirty ? 4'b0001
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: port.clear & port.clearWb & port.clearIdx & tagV[1] & tagOut[1].dirty ? 4'b0010
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: port.clear & port.clearWb & port.clearIdx & tagV[2] & tagOut[2].dirty ? 4'b0100
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: port.clear & port.clearWb & port.clearIdx & tagV[3] & tagOut[3].dirty ? 4'b1000
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// Normal mode
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: tagV[0] == 0 ? 4'b0001
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: tagV[1] == 0 ? 4'b0010
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: tagV[2] == 0 ? 4'b0100
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@ -164,8 +174,11 @@ module DCache (
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: nowLRU[1] == 0 ? 4'b0010
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: nowLRU[2] == 0 ? 4'b0100
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: 4'b1000;
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assign wen = port.clear & port.clearIdx ? 4'b1111
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: hit ? hitWay : victim;
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assign wen = port.clear & port.clearIdx & ~port.clearWb ? 4'b1111 // Index Invalidate
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: port.clear & ~port.clearIdx & ~port.clearWb ? hitWay // Hit Invalidate
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: port.clear & port.clearWb ? victim // Writeback Invalidate
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: hit ? hitWay : victim;
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assign port.dirt_valid = (state == LOOKUP)
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& |{tagV & {tagOut[3].dirty, tagOut[2].dirty, tagOut[1].dirty, tagOut[0].dirty} & victim};
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@ -182,7 +195,8 @@ module DCache (
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| (victim[3] ? dataOut[3] : `DC_DATA_LENGTH'b0);
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// Update LRU
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assign nextLRU = {
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assign nextLRU = port.clear & port.clearIdx ? nowLRU :
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{
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wen[3] | nowLRU[3] & ~&{nowLRU | wen},
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wen[2] | nowLRU[2] & ~&{nowLRU | wen},
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wen[1] | nowLRU[1] & ~&{nowLRU | wen},
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@ -232,10 +246,10 @@ module DCache (
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assign DataRAM2.wen = (bwe1 & wen[2]) | (bwe2 & wen2[2]);
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assign DataRAM3.wen = (bwe1 & wen[3]) | (bwe2 & wen2[3]);
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// 写数据
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assign TagRAM0.wdata = {port.tag1, port.wvalid, ~port.clear};
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assign TagRAM1.wdata = {port.tag1, port.wvalid, ~port.clear};
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assign TagRAM2.wdata = {port.tag1, port.wvalid, ~port.clear};
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assign TagRAM3.wdata = {port.tag1, port.wvalid, ~port.clear};
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assign TagRAM0.wdata = {port.tag1, port.wvalid, ~(port.clear | bwe2 & clear)};
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assign TagRAM1.wdata = {port.tag1, port.wvalid, ~(port.clear | bwe2 & clear)};
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assign TagRAM2.wdata = {port.tag1, port.wvalid, ~(port.clear | bwe2 & clear)};
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assign TagRAM3.wdata = {port.tag1, port.wvalid, ~(port.clear | bwe2 & clear)};
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assign DataRAM0.wdata = state == LOOKUP ? wdata1[0] : wdata2[0];
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assign DataRAM1.wdata = state == LOOKUP ? wdata1[1] : wdata2[1];
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144
src/MMU/MMU.sv
144
src/MMU/MMU.sv
@ -65,7 +65,7 @@ module MMU (
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DR_WA,
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DR_WD1, DR_WD2, DR_WD3, DR_WD4,
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DR_REFILL,
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DR_ICACHE, DR_CACHE, DR_CACHE_REFILL, DR_CACHE_CLEAR, DR_CACHE_REQ
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DR_ICACHE, DR_CACHE, DR_CACHE_REFILL, DR_CACHE_REQ
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} drstate_t;
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typedef enum bit [2:0] {
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@ -98,7 +98,7 @@ module MMU (
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word_t iD1, iD2, iD3, iD4, iD5, iD6, iD7;
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logic diReq;
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CacheOp_t cacheOp1, cacheOp2;
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CacheOp_t cacheOp1;
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word_t dVA1, diPA;
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// ================================
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@ -297,7 +297,9 @@ module MMU (
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logic [127:0] ddData1;
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// D-Cache Clear
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logic dClrValid, dClrRv, dClrReq;
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logic dClrRv, dClrReq;
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logic dDirtValid;
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logic dCEn, dCClear, dCCached;
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// ============================
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// ======== dFlip-Flop ========
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@ -312,7 +314,9 @@ module MMU (
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ffen #(4) dwstrb_ff (clk, data.wstrb, dEn2, dWstrb1);
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ffen #(32) dwdata_ff (clk, data.wdata, dEn2, dWdata1);
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ffen #(3) cache_op_ff (clk, cacheOp[2:0], dEn, cacheOp1[2:0]);
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ffen #(3) cache_op2_ff (clk, cacheOp1[2:0], dEn2, cacheOp2[2:0]);
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ffen #(1) dDirtValid_ff (clk, dc.dirt_valid, dEn2, dDirtValid);
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ffenr #(1) dCCached_ff (clk, dCClear | rst, 1'b1, dCEn, dCCached);
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// =================================
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// ======== drState Machine ========
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@ -329,32 +333,44 @@ module MMU (
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always_comb begin
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dEn = 0;
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dEn2 = 0;
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dCEn = 0;
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dCClear = 0;
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drNextState = drState;
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data.data_ok = 0;
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rdata_axi.req = 0;
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// D-Cache 清除功能 (与 req 一起发送)
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dc.clear = 0;
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dc.clearIdx = 0;
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dc.clearWb = 0;
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dClrValid = 0;
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// 直接发送 dc.rvalid
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dClrRv = 0;
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// 直接发送 dc.req
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dClrReq = 0;
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case (drState)
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DR_IDLE: begin
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if (diReq) drNextState = DR_ICACHE;
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else if (dReq1 & cacheOp1[2] & (dCached1 | cacheOp1[1])) begin
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if (cacheOp2[0]) begin
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// Do not write back
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// dc.valid = dc.wvalid = 1;
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dClrValid = 1;
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dc.clear = 1;
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dc.clearIdx = cacheOp2[1];
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drNextState = DR_CACHE_REFILL;
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else if (dReq1 & cacheOp1[2] & (dCached1 | dCCached | cacheOp1[1])) begin
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if (cacheOp1[0]) begin
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// 不需要写回的情况
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// D-Cache 状态机处于 Lookup 阶段
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dc.clear = 1; // 发送清除
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dc.clearIdx = cacheOp1[1]; // 清除时清除整行或者命中对象
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drNextState = DR_CACHE_REFILL; // 进入 REFILL 等候写入完成
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end else begin
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// WriteBack
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dc.clearWb = 1;
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drNextState = DR_CACHE;
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dEn2 = 1;
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// 需要写回
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// 此时 D-Cache 状态机处于 Lookup 状态
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// 可能是: 1. CACHE 请求第一次发送
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// 2. Index Writeback 清除一路后返回
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dc.clear = 1; // 发送清除
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dc.clearIdx = cacheOp1[1]; // 清除时清除整行或者命中对象
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dc.clearWb = 1; // 需要写回的清除
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drNextState = DR_CACHE; // 进入 DR_CACHE 等候写入完成
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dEn2 = 1; // 二阶段
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dCEn = 1; // 缓存 dCached1
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end
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end else if (dReq1 & cacheOp1[2]) begin
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// avoid deadlock when address is uncached
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drNextState = DR_CACHE_REFILL;
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end else if (~dValid1) dEn = 1;
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else begin
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dEn2 = 1;
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@ -422,34 +438,31 @@ module MMU (
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end
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DR_CACHE: begin
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// WriteBack
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// Clear By Index or Address
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// D-Cache: state == REPLACE
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if (wdata_ok) begin
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if (cacheOp2[1]) begin
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drNextState = DR_CACHE_CLEAR;
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dClrRv = 1; // 直接发送 dc.rvalid 通知可写
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// Why cann't I send dc.clear HERE ???
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// dc.clear = 1;
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if (cacheOp1[1]) begin
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// Clear by Index
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if (dDirtValid)
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drNextState = DR_CACHE_REQ; // 重新进入准备其它路的清除
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else
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drNextState = DR_CACHE_REFILL; // 清除完了
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end else begin
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dClrRv = 1;
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dc.clear = 1;
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drNextState = DR_CACHE_REFILL;
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// Clear by Address
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drNextState = DR_CACHE_REFILL; // 进入 REFILL 等候写入完成
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end
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// drNextState = DR_CACHE_CLEAR;
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end
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end
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DR_CACHE_REFILL: begin
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// avoid deadlock
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dCClear = 1;
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dEn = 1;
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drNextState = DR_IDLE;
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data.data_ok = 1;
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end
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DR_CACHE_CLEAR: begin
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// deal with timing loop
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dClrRv = 1;
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dc.clear = 1;
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drNextState = DR_CACHE_REQ;
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end
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DR_CACHE_REQ: begin
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// deal with timing loop
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dClrReq = 1; // use dClrReq to start a new D-Cache req
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dClrReq = 1;
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drNextState = DR_IDLE;
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end
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endcase
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@ -459,31 +472,6 @@ module MMU (
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// ========== dFunction ==========
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// ================================
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/*
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* D-Cache Cache 指令实现备注
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* Cache 指令当成写指令处理
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* TLB 转换请求和 D-Cache 请求与普通访存一致
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* dc.req 在 I-Cache Cache 指令发生时为0
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* dwState 和 dwaState 需判断是否是 CACHE 指令且是否允许写回
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* 屏蔽 dAddressError 和 TLBModified 且只有在 Address 类型请求下允许 TLBRefill 和 TLBInvalid
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* Index WriteBack 转换成 Hit WriteBack(s) + Index Invalid
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*/
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/* 状态
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D-Cache:
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IDLE <- dc.req + dc.index
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LOOKUP <- dc.tag1: Lookup模式下需要传入正确的tag1
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dc.valid: 1
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dc.wvalid: 1
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dc.clear: Hit Invalid and Index Invalid
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dc.clearIdx: Hit Invalid or Index Invalid
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dc.clearWb: 是否需要写回
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-> dc.dirt_valid
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dc.dirt_addr
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dc.dirt_data
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REPLACE <- dc.rvalid
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dc.clear: same cycle as dc.rvalid
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*/
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assign dVA = data.addr;
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assign diReq = dReq1 & ~cacheOp1[2] & |cacheOp1[1:0];
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assign dcReq1 = dReq1 & (cacheOp1 == CNOP | cacheOp1[2]); // exclude I-Cache clear
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@ -534,7 +522,7 @@ module MMU (
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// do not request when handling CACHE instruction on I-Cache
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assign dc.req = dClrReq | dEn & (cacheOp[2] | ~|cacheOp[1:0]);
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assign dc.valid = dClrValid | dValid1 & dCached1;
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assign dc.valid = dValid1 & dCached1 | dc.clear;
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assign dc.index = dEn ? dVA[`DC_TAGL-1:`DC_INDEXL] : dVA1[`DC_TAGL-1:`DC_INDEXL];
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assign dc.tag1 = dEn2 ? dPA1[31:`DC_TAGL] : dPA2[31:`DC_TAGL];
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assign dc.sel1 = dEn2 ? dPA1[3:2] : dPA2[3:2];
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@ -574,12 +562,12 @@ module MMU (
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case (dwState)
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DW_IDLE: begin
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if (dEn2 & (~dCached1 & data.wr
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| dCached1 & dc.dirt_valid
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& (~cacheOp1[2] | ~cacheOp1[0]) // WriteOnly 不允许写回
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& (~dc.hit | cacheOp1[2] & ~cacheOp1[0]) // Writeback 或一般情况
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if (dEn2 & (~(dCached1 | dCEn) & data.wr
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| (dCached1 | dCEn) & dc.dirt_valid
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& (~cacheOp1[2] | ~cacheOp1[0]) // WriteOnly 不允许写回
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& (~dc.hit | cacheOp1[2] & ~cacheOp1[0]) // Writeback 或一般情况
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)) begin
|
||||
if (dCached1) begin
|
||||
if (dCached1 | dCEn) begin
|
||||
wdata_axi.wdata = dc.dirt_data[31:0];
|
||||
wdata_axi.wstrb = 4'b1111;
|
||||
wdata_axi.wvalid = 1'b1;
|
||||
@ -592,7 +580,7 @@ module MMU (
|
||||
|
||||
if (~wdata_axi.wready) dwNextState = DW_WD1;
|
||||
else begin
|
||||
if (dCached1) dwNextState = DW_WD2;
|
||||
if (dCached1 | dCEn) dwNextState = DW_WD2;
|
||||
else begin
|
||||
if (~wdata_axi.data_ok) dwNextState = DW_WB;
|
||||
else begin
|
||||
@ -605,7 +593,7 @@ module MMU (
|
||||
end
|
||||
end
|
||||
DW_WD1: begin
|
||||
if (dCached2) begin
|
||||
if (dCached2 | dCCached) begin
|
||||
wdata_axi.wdata = ddData1[31:0];
|
||||
wdata_axi.wstrb = 4'b1111;
|
||||
wdata_axi.wvalid = 1'b1;
|
||||
@ -617,7 +605,7 @@ module MMU (
|
||||
end
|
||||
|
||||
if (wdata_axi.wready) begin
|
||||
if (dCached2) dwNextState = DW_WD2;
|
||||
if (dCached2 | dCCached) dwNextState = DW_WD2;
|
||||
else begin
|
||||
if (~wdata_axi.data_ok) dwNextState = DW_WB;
|
||||
else begin
|
||||
@ -652,7 +640,7 @@ module MMU (
|
||||
if (~wdata_axi.data_ok) dwNextState = DW_WB;
|
||||
else begin
|
||||
// fixme: AXI3 wait WA
|
||||
if (drState == DR_REFILL | drState == DR_CACHE_REFILL) dwNextState = DW_IDLE;
|
||||
if (drState == DR_REFILL | drState == DR_CACHE_REFILL | drState == DR_CACHE_REQ) dwNextState = DW_IDLE;
|
||||
else dwNextState = DW_WAITR;
|
||||
end
|
||||
end
|
||||
@ -661,12 +649,12 @@ module MMU (
|
||||
// TODO: goto IDLE on failure
|
||||
if (wdata_axi.data_ok) begin
|
||||
// fixme: AXI3 wait WA
|
||||
if (drState == DR_REFILL | drState == DR_CACHE_REFILL) dwNextState = DW_IDLE;
|
||||
if (drState == DR_REFILL | drState == DR_CACHE_REFILL | drState == DR_CACHE_REQ) dwNextState = DW_IDLE;
|
||||
else dwNextState = DW_WAITR;
|
||||
end
|
||||
end
|
||||
DW_WAITR: begin
|
||||
if (drState == DR_REFILL | drState == DR_CACHE_REFILL) dwNextState = DW_IDLE;
|
||||
if (drState == DR_REFILL | drState == DR_CACHE_REFILL | drState == DR_CACHE_REQ) dwNextState = DW_IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
@ -687,10 +675,10 @@ module MMU (
|
||||
|
||||
case (dwaState)
|
||||
DWA_IDLE: begin
|
||||
if (dEn2 & (~dCached1 & data.wr
|
||||
| dCached1 & dc.dirt_valid
|
||||
& (~cacheOp1[2] | ~cacheOp1[0]) // WriteOnly 不允许写回
|
||||
& (~dc.hit | cacheOp1[2] & ~cacheOp1[0]) // Writeback 或一般情况
|
||||
if (dEn2 & (~(dCached1 | dCEn) & data.wr
|
||||
| (dCached1 | dCEn) & dc.dirt_valid
|
||||
& (~cacheOp1[2] | ~cacheOp1[0]) // WriteOnly 不允许写回
|
||||
& (~dc.hit | cacheOp1[2] & ~cacheOp1[0]) // Writeback 或一般情况
|
||||
)) begin
|
||||
wdata_axi.req = 1'b1;
|
||||
if (~wdata_axi.addr_ok) dwaNextState = DWA_WA;
|
||||
@ -724,10 +712,10 @@ module MMU (
|
||||
// ========== dwFunction ==========
|
||||
// ================================
|
||||
|
||||
assign wdata_axi.addr = (dEn2 ? dCached1 : dCached2) ? (dwaState == DWA_IDLE) ? dc.dirt_addr : ddAddr1 : dEn2 ? dPA1 : dPA2;
|
||||
assign wdata_axi.len = (dEn2 ? dCached1 : dCached2) ? 4'b0011 : 4'b0000;
|
||||
assign wdata_axi.size = (dEn2 ? dCached1 : dCached2) ? 3'b010 : {1'b0, dSize1};
|
||||
assign dc.wvalid = dClrValid | dEn2 ? data.wr : dwr1;
|
||||
assign wdata_axi.addr = ((dEn2 ? dCached1 : dCached2) | dCEn) ? (dwaState == DWA_IDLE) ? dc.dirt_addr : ddAddr1 : dEn2 ? dPA1 : dPA2;
|
||||
assign wdata_axi.len = ((dEn2 ? dCached1 : dCached2) | dCEn) ? 4'b0011 : 4'b0000;
|
||||
assign wdata_axi.size = ((dEn2 ? dCached1 : dCached2) | dCEn) ? 3'b010 : {1'b0, dSize1};
|
||||
assign dc.wvalid = dEn2 ? data.wr : dwr1;
|
||||
assign dc.wdata = dEn2 ? data.wdata : dWdata1;
|
||||
assign dc.wstrb = dEn2 ? data.wstrb : dWstrb1;
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user