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4f7fe2adf2
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feat: MU rewrite 2
TLB Support
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2022-07-27 18:11:54 +08:00 |
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9ce588757d
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feat: MU rewrite 1
1. ALU format
2. FIX hazard (MOVN / MOVZ)
3. verilator support
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2022-07-27 15:07:16 +08:00 |
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Qiu Jiahao
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e569965556
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refactor MU
Co-authored-by: Paul <panyuxuan@hotmail.com>
Co-authored-by: cxy004 <cxy004@qq.com>
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2022-07-16 08:44:29 +08:00 |
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Qiu Jiahao
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eb9f835e6b
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refactor cache
Co-authored-by: cxy004 <cxy004@qq.com>
Co-authored-by: Paul <panyuxuan@hotmail.com>
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2022-06-21 21:52:06 +08:00 |
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b3238b0f86
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Merge branch 'soc_top'
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2022-05-24 21:51:02 +08:00 |
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a2f8fdae9b
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clean up
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2021-10-14 22:31:25 +08:00 |
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00170784d0
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Merge branch 'fix/cache' into soc_top
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2021-10-14 22:20:31 +08:00 |
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24613eeade
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Revert "refactor DCache"
This reverts commit fa0f195d17.
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2021-09-30 22:48:27 +08:00 |
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fa0f195d17
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refactor DCache
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2021-09-30 22:45:28 +08:00 |
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c4942661dc
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refactor cache inst on I-Cache
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2021-09-27 16:58:22 +08:00 |
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4facc2dd10
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enhanced test cases
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2021-09-24 20:45:55 +08:00 |
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aca8490ef2
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deal with verilator
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2021-09-24 16:37:47 +08:00 |
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8c7272e1f2
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add model
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2021-09-22 23:07:13 +08:00 |
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a5192eb4d8
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update README.md
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2021-09-22 22:29:52 +08:00 |
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62b26e3ab2
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fix trap
add testcases
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2021-09-22 16:26:40 +08:00 |
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de354f73d0
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fix Datapath.sv
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2021-09-22 13:52:43 +08:00 |
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75a62cfc37
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try add trap
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2021-09-22 13:41:09 +08:00 |
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a1bbfa0a0c
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make linter happy
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2021-09-21 17:15:30 +08:00 |
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ab1b2ad13d
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fix CP0
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2021-09-12 19:48:56 +08:00 |
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a0d3367f34
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update ALU and test
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2021-09-07 19:53:53 +08:00 |
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29c6e16682
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try add MOVZ, MOVN
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2021-09-07 19:24:34 +08:00 |
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7e85ca17e3
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refactor D-Cache CACHE inst
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2021-09-06 22:36:37 +08:00 |
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0cd3d9007e
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1. fix D-Cache clear by index
2. fix testcases
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2021-09-06 09:27:22 +08:00 |
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9df689ed7a
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refactor CACHE inst on D-CACHE
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2021-09-05 23:59:23 +08:00 |
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f8d7b7b0c6
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1. fix exceptions about CACHE inst on D-Cache
2. fix D-Cache control signals
3. fix I-Cache tag1 signal
4. fix I-Cache clear index logic
5. enhance D-Cache tests
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2021-09-05 13:06:35 +08:00 |
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1f2d7f6f3c
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1. fix deadlock on continuous CACHE inst
2. enhance the testcases
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2021-09-04 21:07:00 +08:00 |
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e08ded2242
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Test Passed? maybe
1. fix timing loop
2. fix multi driven
3. fix CACHE I-Cache Index logic
4. fix testcase
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2021-09-04 16:31:25 +08:00 |
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fa0c8ece07
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1. fix index addr
2. add n99 I-Cache CACHE test
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2021-09-03 22:16:59 +08:00 |
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2143cbe630
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try add I-Cache's CACHE inst
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2021-09-03 21:23:32 +08:00 |
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17f64e1f2f
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1. add cache (D-Cache Address) inst
2. fix bug in ALR
3. fix bug in MMU and DCache
4. Register File rst
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2021-09-02 19:20:19 +08:00 |
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f256abd248
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add control signals
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2021-09-02 19:05:23 +08:00 |
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ed49e734d8
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update Controller and Datapath
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2021-09-02 11:05:33 +08:00 |
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3dffdae575
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try add D-Cache's CACHE inst
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2021-09-01 23:12:58 +08:00 |
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53c0c018bb
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fix bug in decode
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2021-08-31 21:11:59 +08:00 |
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b0a9cd857c
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fix bug in MADD MADDU MSUB MSUBU
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2021-08-31 20:43:49 +08:00 |
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0269228c3c
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add test
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2021-08-31 19:32:39 +08:00 |
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966b7b6223
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add control signals
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2021-08-31 18:30:03 +08:00 |
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9be2310177
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add MADD, MADDU, MSUB, MSUBU
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2021-08-31 18:29:27 +08:00 |
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2f22688aca
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update README.md and fix bug in inst test
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2021-08-30 15:59:21 +08:00 |
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94ab693971
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update gadgets
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2021-08-30 14:23:04 +08:00 |
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0b872c9b7c
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add sync pref as nop
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2021-08-30 13:11:40 +08:00 |
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eea7b6bbda
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add lwl lwr swl swr test cases
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2021-08-29 20:17:42 +08:00 |
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cf9d3e8ed0
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fix bug in SWR
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2021-08-29 20:16:57 +08:00 |
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6cc760be79
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SWL/SWR: update Datapath.sv and Gadgets.sv
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2021-08-29 17:14:47 +08:00 |
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1f94aebd9d
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update control signals for swl/swr
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2021-08-29 16:47:34 +08:00 |
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62b8efb8e3
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lwl/lwr: fix bug in addr and strberror
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2021-08-27 22:25:42 +08:00 |
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54c6794a77
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add LWL and LWR
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2021-08-26 18:32:55 +08:00 |
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1ad35234dc
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txt add tlbwr
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2021-08-26 17:04:09 +08:00 |
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1a51af6827
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fix ADES
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2021-08-25 22:00:59 +08:00 |
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8d039f4327
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handle CpU exception
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2021-08-25 20:59:32 +08:00 |
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