fix bug in SWR
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README.md
26
README.md
@ -31,9 +31,9 @@ Our awesome `MIPS` CPU written in `SystemVerilog` for Loongson Cup
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| Status | Instruction | Type | Tier | Comment |
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| :----------------: | :---------: | :------: | :--: | :-------------------------------------- |
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| :clock3: | `Cache` | `SYS` | 2 | |
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| :clock3: | `PREF` | `SYS` | 1 | Treat as `NOP` |
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| :clock3: | `SYNC` | `SYS` | 1 | Treat as `NOP` (We're strongly ordered) |
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| :clock3: | `WAIT` | `SYS` | 3 | |
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| :hourglass: | `PREF` | `SYS` | 1 | Treat as `NOP` |
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| :hourglass: | `SYNC` | `SYS` | 1 | Treat as `NOP` (We're strongly ordered) |
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| :clock3: | `WAIT` | `SYS` | 2 | |
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| :clock3: | `TEQ` | `SYS` | 2 | |
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| :clock3: | `TEQI` | `SYS` | 2 | |
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| :clock3: | `TGE` | `SYS` | 2 | |
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@ -52,16 +52,16 @@ Our awesome `MIPS` CPU written in `SystemVerilog` for Loongson Cup
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| :clock3: | `MADDU` | `ARITH` | 2 | |
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| :clock3: | `MSUB` | `ARITH` | 2 | |
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| :clock3: | `MSUBU` | `ARITH` | 2 | |
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| :clock3: | `MOVN` | `ARITH` | 1 | |
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| :clock3: | `MOVZ` | `ARITH` | 1 | |
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| :clock3: | `LL` | `MEM` | 3 | |
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| :heavy_check_mark: | `LWL` | `MEM` | 1 | 需要补充测试 |
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| :heavy_check_mark: | `LWR` | `MEM` | 1 | 需要补充测试 |
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| :clock3: | `SC` | `MEM` | 3 | |
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| :hourglass: | `SWL` | `MEM` | 1 | |
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| :hourglass: | `SWR` | `MEM` | 1 | |
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| :clock3: | `MOVF` | `FP` | 2 | |
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| :clock3: | `MOVT` | `FP` | 2 | |
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| :clock3: | `MOVN` | `ARITH` | 2 | |
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| :clock3: | `MOVZ` | `ARITH` | 2 | |
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| :hourglass: | `LL` | `MEM` | 1 | Treat as `LW` |
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| :heavy_check_mark: | `LWL` | `MEM` | 1 | |
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| :heavy_check_mark: | `LWR` | `MEM` | 1 | |
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| :hourglass: | `SC` | `MEM` | 1 | Treat as `SW` |
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| :heavy_check_mark: | `SWL` | `MEM` | 1 | |
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| :heavy_check_mark: | `SWR` | `MEM` | 1 | |
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| :clock3: | `MOVF` | `FP` | 3 | |
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| :clock3: | `MOVT` | `FP` | 3 | |
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| :clock3: | `BEQL` | `BRANCH` | 3 | |
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| :clock3: | `BGEZALL` | `BRANCH` | 3 | |
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| :clock3: | `BGEZL` | `BRANCH` | 3 | |
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@ -127,6 +127,7 @@ module memoutput (
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output word_t wdata,
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output logic [3:0] wstrb
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);
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// TODO: wdata fill zero or replica
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always_comb
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casez (size)
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2'b11: begin
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@ -136,10 +137,26 @@ module memoutput (
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2'b10: begin
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wdata = data;
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case (addr)
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2'b11: begin wstrb = alr[0] ? 4'b1111 : 4'b1000; end
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2'b10: begin wstrb = alr[0] ? 4'b0111 : 4'b1100; end
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2'b01: begin wstrb = alr[0] ? 4'b0011 : 4'b1110; end
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2'b00: begin wstrb = alr[0] ? 4'b0001 : 4'b1111; end
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2'b11: begin
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wstrb = alr[0] ? 4'b1111 : 4'b1000;
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wdata = alr[0] ? data
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: {data[7:0], data[31:8]};
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end
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2'b10: begin
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wstrb = alr[0] ? 4'b0111 : 4'b1100;
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wdata = alr[0] ? {data[7:0], data[31:8]}
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: {data[15:0], data[31:16]};
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end
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2'b01: begin
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wstrb = alr[0] ? 4'b0011 : 4'b1110;
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wdata = alr[0] ? {data[15:0], data[31:16]}
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: {data[23:0], data[31:24]};
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end
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2'b00: begin
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wstrb = alr[0] ? 4'b0001 : 4'b1111;
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wdata = alr[0] ? {data[23:0], data[31:24]}
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: data;
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end
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endcase
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end
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2'b01: begin
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