Magically Improved Pipeline Stages

Our awesome MIPS CPU written in SystemVerilog for Loongson Cup

.
├── resources                <-- 资源包
│   └── 2021                 <-- 2021年资源包
│       ├── cpu132_gettrace  <-- 性能测试基准(gs132)
│       ├── soc_axi_func     <-- AXI功能测试
│       ├── soc_axi_perf     <-- AXI性能测试
│       ├── soc_axi_system   <-- AXI系统测试
│       └── soft             <-- 测试用程序
│           ├── func         <-- 功能测试
│           ├── memory_game  <-- 记忆游戏
│           └── perf_func    <-- 性能测试
├── src                      <-- CPU设计代码
│   ├── AXI                  <-- AXI总线交互
│   ├── Cache                <-- Cache
│   ├── Core                 <-- CPU核心
│   ├── CP0                  <-- CP0协处理器
│   ├── include              <-- 头文件
│   ├── IP                   <-- 用到的IP
│   ├── MMU                  <-- 地址转换单元
│   └── testbench            <-- 测试脚本
└── tools                    <-- controller生成器

TODO & Notice

• 特权模式
  • CP0寄存器Status.UM ✔️
  • 访存异常(考虑in_kernel状态切换带来的冒险) ✔️
  • 特权指令异常 ✔️
• 浮点运算单元
  • 做一个真的FPU ❌
  • 浮点运算指令报Coprocessor Unusable，同时CP0中新增Cause.CE 🕒
• 新增指令

Status	Instruction	Type	Tier	Comment
🕒	Cache	SYS	3
🕒	PREF	SYS	1	Treat as NOP
🕒	SYNC	SYS	1	Treat as NOP (We're strongly ordered)
🕒	WAIT	SYS	3
🕒	TEQ	SYS	2
🕒	TEQI	SYS	2
🕒	TGE	SYS	2
🕒	TGEI	SYS	2
🕒	TGEIU	SYS	2
🕒	TGEU	SYS	2
🕒	TLT	SYS	2
🕒	TLTI	SYS	2
🕒	TLTIU	SYS	2
🕒	TLTU	SYS	2
🕒	TNE	SYS	2
🕒	TNEI	SYS	2
🕒	CLO	ARITH	2	RT == RD
🕒	CLZ	ARITH	2	RT == RD
🕒	MADD	ARITH	2
🕒	MADDU	ARITH	2
🕒	MSUB	ARITH	2
🕒	MSUBU	ARITH	2
🕒	MOVN	ARITH	1
🕒	MOVZ	ARITH	1
🕒	LL	MEM	3
⌛	LWL	MEM	1
:hour	LWR	MEM	1
🕒	SC	MEM	3
⌛	SWL	MEM	1
⌛	SWR	MEM	1
🕒	MOVF	FP	2
🕒	MOVT	FP	2
🕒	BEQL	BRANCH	3
🕒	BGEZALL	BRANCH	3
🕒	BGEZL	BRANCH	3
🕒	BGTZL	BRANCH	3
🕒	BLEZL	BRANCH	3
🕒	BLTZALL	BRANCH	3
🕒	BLTZL	BRANCH	3
🕒	BNEL	BRANCH	3