Magically Improved Pipeline Stages

Our awesome MIPS CPU written in SystemVerilog for Loongson Cup

.
├── resources                <-- 资源包
├── src                      <-- CPU设计代码
│   ├── AXI                  <-- AXI总线交互
│   ├── Cache                <-- Cache
│   ├── Core                 <-- CPU核心
│   ├── CP0                  <-- CP0协处理器
│   ├── include              <-- 头文件
│   ├── IP                   <-- 用到的IP
│   └── MMU                  <-- 地址转换单元
└── tools                    <-- 控制信号生成器

Progress

• 特权模式
  • CP0寄存器Status.UM ✔️
  • 访存异常(考虑in_kernel状态切换带来的冒险) ✔️
  • 特权指令异常 ✔️
• 浮点运算单元
  • 做一个真的FPU ❌
  • 浮点运算指令报Coprocessor Unusable，同时CP0中新增Cause.CE 🕒
• 新增指令

Status	Instruction	Type	Tier	Comment
🕒	Cache	SYS	2
⌛	PREF	SYS	1	Treat as NOP
⌛	SYNC	SYS	1	Treat as NOP (We're strongly ordered)
🕒	WAIT	SYS	2
🕒	TEQ	SYS	2
🕒	TEQI	SYS	2
🕒	TGE	SYS	2
🕒	TGEI	SYS	2
🕒	TGEIU	SYS	2
🕒	TGEU	SYS	2
🕒	TLT	SYS	2
🕒	TLTI	SYS	2
🕒	TLTIU	SYS	2
🕒	TLTU	SYS	2
🕒	TNE	SYS	2
🕒	TNEI	SYS	2
🕒	CLO	ARITH	2	RT == RD
🕒	CLZ	ARITH	2	RT == RD
🕒	MADD	ARITH	2
🕒	MADDU	ARITH	2
🕒	MSUB	ARITH	2
🕒	MSUBU	ARITH	2
🕒	MOVN	ARITH	2
🕒	MOVZ	ARITH	2
⌛	LL	MEM	1	Treat as LW
✔️	LWL	MEM	1
✔️	LWR	MEM	1
⌛	SC	MEM	1	Treat as SW
✔️	SWL	MEM	1
✔️	SWR	MEM	1
🕒	MOVF	FP	3
🕒	MOVT	FP	3
🕒	BEQL	BRANCH	3
🕒	BGEZALL	BRANCH	3
🕒	BGEZL	BRANCH	3
🕒	BGTZL	BRANCH	3
🕒	BLEZL	BRANCH	3
🕒	BLTZALL	BRANCH	3
🕒	BLTZL	BRANCH	3
🕒	BNEL	BRANCH	3