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e4dd24aaf7
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sync
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2023-01-05 17:17:59 +08:00 |
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57b9d66643
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Fix HI/LO
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2022-08-18 18:45:57 +08:00 |
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7c5fef05b0
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Fix EXL related
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2022-08-17 18:09:08 +08:00 |
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ed0ef6461d
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Fix MTHI MTLO Hazard
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2022-08-16 16:44:41 +08:00 |
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caa2171996
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Fix TLB
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2022-08-15 23:41:08 +08:00 |
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7a506ba611
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Fix LRU
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2022-08-14 22:05:12 +08:00 |
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21ff0f0c19
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update
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2022-08-13 15:40:54 +08:00 |
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d04ff42702
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nscscc2022 preliminary
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2022-08-07 10:34:02 +08:00 |
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cxy004
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429f7e55cb
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spec
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2022-08-05 14:48:55 +08:00 |
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cxy004
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9048a4749d
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2alu without overflow
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2022-08-05 00:32:08 +08:00 |
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f4ac7199c9
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Merge remote-tracking branch 'origin/2alu' into next-crazy
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2022-08-04 22:48:36 +08:00 |
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054e4611de
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update CpU and TLB
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2022-08-04 21:13:23 +08:00 |
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cb31fcd0db
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Configurable [l,s]w[l,r]
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2022-08-04 20:25:43 +08:00 |
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796c83b72a
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adjust mul/div
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2022-08-04 19:54:40 +08:00 |
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8db46ab67b
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fix DCache
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2022-08-04 18:41:16 +08:00 |
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dfa2e628a2
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Minimize CP0 when TLB is disabled
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2022-08-04 16:43:29 +08:00 |
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baa2bb049f
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Configurable MADD
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2022-08-04 16:15:18 +08:00 |
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acc50f3c89
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fix bug
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2022-08-04 15:14:07 +08:00 |
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cxy004
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8d36e89a21
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2alu linux fix (pmon?)
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2022-08-04 14:48:57 +08:00 |
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31030d6a84
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Configurable Cache
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2022-08-04 14:44:31 +08:00 |
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bab898db60
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Config1 auto generate
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2022-08-04 13:24:45 +08:00 |
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d31446ae87
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Configurable Cache & Bigger Cache
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2022-08-04 13:00:33 +08:00 |
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cxy004
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cc1988ceba
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2alu tryfix
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2022-08-04 12:40:46 +08:00 |
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d487e8583d
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Update ENABLE_TLB
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2022-08-04 11:53:11 +08:00 |
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cxy004
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101230bd67
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2alu fix
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2022-08-03 18:44:33 +08:00 |
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cxy004
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0183c129bf
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Merge remote-tracking branch 'origin/next' into 2alu
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2022-08-03 14:33:38 +08:00 |
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cxy004
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5392df67ac
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1. mov change
2. 2alu
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2022-08-03 14:28:07 +08:00 |
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02f04a2bf3
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Update MU and DCache
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2022-08-03 14:26:44 +08:00 |
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cxy004
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c2fa121f92
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2alu
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2022-08-03 11:17:07 +08:00 |
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db1aa1d615
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Manual Merge
Co-authored-by: cxy004 <cxy004@qq.com>
Co-authored-by: Hooo1941 <Hooo1941@users.noreply.github.com>
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2022-08-02 11:29:23 +08:00 |
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a7793c6741
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Another big update
1. refactor func test
2. fix CACHE inst
3. CP0 add Context Register
4. fix AXIWriter order
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2022-08-01 22:01:24 +08:00 |
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56cc2e5dcb
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fix: MU wstrb could directly passthrough
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2022-07-29 23:25:14 +08:00 |
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b25fbb5ee1
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fix: multiply model
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2022-07-29 18:48:58 +08:00 |
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bf7ee46645
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feat: reconfigure crossbar
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2022-07-29 18:26:27 +08:00 |
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7b33e4213a
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a big update
1. add test soft
2. modify verilator (TODO: crossbar need to replace)
3. fix CP0: now CU0 is always 1
4. Controller: cacheop
5. Controller: fix TEN
6. mycpu_top fix CP0_i
7. fix AXI.sv
8. fix AXIReader.sv
9. fix AXIWriter.sv: getting the correct data and length
10. MU: fix cache writeback, fix mem data mux, fix writer address, fix read request
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2022-07-29 18:25:58 +08:00 |
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4f7fe2adf2
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feat: MU rewrite 2
TLB Support
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2022-07-27 18:11:54 +08:00 |
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9ce588757d
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feat: MU rewrite 1
1. ALU format
2. FIX hazard (MOVN / MOVZ)
3. verilator support
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2022-07-27 15:07:16 +08:00 |
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Qiu Jiahao
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e569965556
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refactor MU
Co-authored-by: Paul <panyuxuan@hotmail.com>
Co-authored-by: cxy004 <cxy004@qq.com>
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2022-07-16 08:44:29 +08:00 |
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Qiu Jiahao
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eb9f835e6b
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refactor cache
Co-authored-by: cxy004 <cxy004@qq.com>
Co-authored-by: Paul <panyuxuan@hotmail.com>
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2022-06-21 21:52:06 +08:00 |
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b3238b0f86
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Merge branch 'soc_top'
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2022-05-24 21:51:02 +08:00 |
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a2f8fdae9b
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clean up
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2021-10-14 22:31:25 +08:00 |
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00170784d0
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Merge branch 'fix/cache' into soc_top
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2021-10-14 22:20:31 +08:00 |
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24613eeade
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Revert "refactor DCache"
This reverts commit fa0f195d17.
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2021-09-30 22:48:27 +08:00 |
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fa0f195d17
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refactor DCache
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2021-09-30 22:45:28 +08:00 |
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c4942661dc
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refactor cache inst on I-Cache
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2021-09-27 16:58:22 +08:00 |
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4facc2dd10
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enhanced test cases
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2021-09-24 20:45:55 +08:00 |
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aca8490ef2
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deal with verilator
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2021-09-24 16:37:47 +08:00 |
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8c7272e1f2
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add model
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2021-09-22 23:07:13 +08:00 |
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a5192eb4d8
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update README.md
|
2021-09-22 22:29:52 +08:00 |
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62b26e3ab2
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fix trap
add testcases
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2021-09-22 16:26:40 +08:00 |
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