2alu without overflow
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cxy004
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f4ac7199c9
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9048a4749d
@ -41,8 +41,8 @@ module Controller (
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assign ctrl.ERET = ~inst[31] & inst[30] & inst[4];
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assign ctrl.OFA = ~inst[26] & ~inst[30] & (~inst[29] & ~inst[31] & ~inst[28] & ~inst[27] & inst[5] & ~inst[0] & ~inst[4] & ~inst[2] & ~inst[3] | inst[29] & ~inst[27] & ~inst[31] & ~inst[28]);
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assign ctrl.ES = ~inst[31] & ~inst[27] & (~inst[30] & ~inst[29] & (~inst[28] & ~inst[26] & (~inst[5] & ~inst[4] & inst[3] & ~inst[2] & inst[1] | inst[4] & (inst[5] | inst[3])) | ~inst[28] & inst[26] & inst[19]) | inst[30] & inst[29]) | inst[31] & ~inst[30];
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assign ctrl.ET = ~inst[27] & ~inst[26] & (~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & (~inst[5] & ~inst[4] & inst[3] & ~inst[2] & inst[1] | inst[4] & (inst[5] | inst[3])) | inst[30] & inst[29]);
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assign ctrl.ES = ~inst[31] & ~inst[27] & (~inst[30] & ~inst[29] & ~inst[28] & (~inst[26] & (~inst[4] & ~inst[2] & (~inst[5] & inst[3] & inst[1] | inst[5] & ~inst[3] & ~inst[0]) | inst[4] & (inst[5] | inst[3])) | inst[26] & inst[19]) | inst[29] & (inst[30] | ~inst[28] & ~inst[26])) | inst[31] & ~inst[30];
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assign ctrl.ET = ~inst[27] & ~inst[26] & (~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & (~inst[4] & ~inst[2] & (~inst[5] & inst[3] & inst[1] | inst[5] & ~inst[3] & ~inst[0]) | inst[4] & (inst[5] | inst[3])) | inst[30] & inst[29]);
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assign ctrl.ES2 = ~inst[30] & ~inst[28] & ~inst[27] & ~inst[26] & (inst[5] | ~inst[3] & inst[2]) | inst[29];
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assign ctrl.ET2 = ~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & (inst[5] | ~inst[4] & ~inst[3]);
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assign ctrl.DS = ~inst[26] & (~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[4] & inst[3] & ~inst[2] & ~inst[1] | ~inst[31] & ~inst[29] & inst[28]) | ~inst[31] & ~inst[29] & inst[26] & (inst[28] | ~inst[27] & ~inst[19]);
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@ -137,10 +137,12 @@ module Datapath (
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logic E_I0_Overflow;
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WCtrl_t E_I0_NowWCtrl;
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logic E_I0_NowExcValid;
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logic E_I0_NowExcValidWithoutOF;
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logic E_I0_PrevExcValid;
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logic [4:0] E_I0_PrevExcCode;
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logic E_I0_PrevERET;
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logic E_I0_PrevREFILL;
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logic E_I0_ExcValidWithoutOF;
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word_t E_I1_A;
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word_t E_I1_B;
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@ -209,9 +211,6 @@ module Datapath (
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word_t M_I0_B;
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logic M_I0_ALUvalid;
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logic M_I0_Overflow;
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logic M_I0_NowExcValid;
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logic M_I0_PrevExcValid;
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logic [4:0] M_I0_PrevExcCode;
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logic M_I0_DIV_valid;
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word_t M_I0_DIVH;
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@ -308,7 +307,7 @@ module Datapath (
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assign rstD = D_IA_valid & (D.IA.B & D.IA.BGO | D.IA.JR | D.IA.J) & D_IB_valid & D_readygo;
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assign rstM = C0.cpu_exception.ExcValid;
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assign PF_go = ~D.IA_ExcValid & ~D.IB_ExcValid & ~E.I0.ExcValid & ~E_I1_ExcValidWithoutOF
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assign PF_go = ~D.IA_ExcValid & ~D.IB_ExcValid & ~E_I0_ExcValidWithoutOF & ~E_I1_ExcValidWithoutOF
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& (~D_IB_valid | ~D.IA.JR | PF_pcjr[1:0] == 2'b00);
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assign fetch.req = M_exception.ExcValid
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| PF_go & (~D_IB_valid & ~fetch.data_ok | (~D.IA.BJRJ | D_readygo)
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@ -623,6 +622,13 @@ module Datapath (
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// end
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// `endif
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// `ifdef SIMULATION_VERILATOR
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// always_ff @(posedge clk) begin
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// $display("<perf> stall = %d, hazard = %d, fetch = %d, mem = %d </perf>",
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// 2 - (D.en0 + D.en1), D_IA_Hazard+D_IB_Hazard, {(fetch.req & ~fetch.addr_ok), 1'b0}, {(mem.req & ~mem.addr_ok), 1'b0});
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// end
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// `endif
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assign D_I0_go = D.A ? D_IB_go : D_IA_go;
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assign D.I0.pc = D.A ? D.IB_pc : D.IA_pc;
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assign D.I0.ExcValid = D.A ? D.IB_ExcValid : D.IA_ExcValid;
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@ -871,11 +877,14 @@ module Datapath (
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);
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// E.Exc
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assign E_I0_NowExcValid = C0_int & E_valid;
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assign E_I0_NowExcValidWithoutOF = C0_int & E_valid;
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assign E_I0_NowExcValid = E_I0_NowExcValidWithoutOF | E_I0_Overflow & E.I0.OFA;
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assign E_I0_ExcValidWithoutOF = E_I0_PrevExcValid | E_I0_NowExcValidWithoutOF;
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assign E.I0.ExcValid = E_I0_PrevExcValid | E_I0_NowExcValid;
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assign E.I0.ERET = E_I0_PrevERET & ~C0_int;
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assign E.I0.REFILL = E_I0_PrevREFILL & ~C0_int;
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assign E.I0.ExcCode = C0_int ? 5'h0 : E_I0_PrevExcCode;
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assign E.I0.ExcCode = C0_int ? 5'h0
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: E_I0_PrevExcValid ? E_I0_PrevExcCode : `EXCCODE_OV;
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assign E_I1_NowExcValidWithoutOF = C0_int & E_valid | E.I1.MCtrl.MR & E_I1_STRBERROR;
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assign E_I1_NowExcValid = E_I1_NowExcValidWithoutOF | E_I1_Overflow & E.I1.OFA;
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@ -890,7 +899,7 @@ module Datapath (
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assign E.I1.BadVAddr = E_I1_PrevExcValid ? E.I1.pc : E.I1.ALUOut;
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assign E_I0_go = ~E_I0_NowExcValid & (~E.A | ~E_I1_NowExcValid);
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assign E_I1_goWithoutOF = ~E_I1_NowExcValidWithoutOF & (E.A | ~E_I0_NowExcValid);
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assign E_I1_goWithoutOF = ~E_I1_NowExcValidWithoutOF & (E.A | ~E_I0_NowExcValidWithoutOF);
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assign E_I1_go = ~E_I1_NowExcValid & (E.A | ~E_I0_NowExcValid);
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// E.I0.ALU
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@ -1081,7 +1090,7 @@ module Datapath (
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{E.I0.ExcValid, E.I0.ERET, E.I0.REFILL, E.I0.ExcCode, E.I0.CE, E.I0.Delay},
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M.en,
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~E_go,
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{M_I0_PrevExcValid, M.I0.ERET, M.I0.REFILL, M_I0_PrevExcCode, M.I0.CE, M.I0.Delay}
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{M.I0.ExcValid, M.I0.ERET, M.I0.REFILL, M.I0.ExcCode, M.I0.CE, M.I0.Delay}
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);
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ffenrc #(1) M_I0_ExcCtrl_ff (
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clk,
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@ -1220,9 +1229,6 @@ module Datapath (
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{dTLBRefillB, dTLBInvalidB, dTLBModifiedB, dAddressErrorB}
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);
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assign M_I0_NowExcValid = M_I0_Overflow & M.I0.OFA;
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assign M.I0.ExcValid = M_I0_PrevExcValid | M_I0_NowExcValid;
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assign M.I0.ExcCode = M_I0_PrevExcValid ? M_I0_PrevExcCode : `EXCCODE_OV;
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assign M_I1_NowExcValid = 0
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`ifdef ENABLE_TLB
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| dTLBRefillB | dTLBInvalidB | dTLBModifiedB | dAddressErrorB
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@ -1242,8 +1248,8 @@ module Datapath (
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: dTLBInvalidB ? M.I1.MCtrl.MWR ? `EXCCODE_TLBS : `EXCCODE_TLBL
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: `EXCCODE_MOD;
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assign M_I0_go = ~M_I0_NowExcValid & (~M.A | ~M_I1_NowExcValid);
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assign M_I1_go = ~M_I1_NowExcValid & ( M.A | ~M_I0_NowExcValid);
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assign M_I0_go = ~M.A | ~M_I1_NowExcValid;
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assign M_I1_go = ~M_I1_NowExcValid;
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assign {M_exception, M_exception_REFILL} = {
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M.I1.ExcValid | M.I0.ExcValid,
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@ -20,9 +20,9 @@
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32'b000000??????????0000000000011001 0 0 0 0 1 1 ? ? 0 0 1 0 // MULTU
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32'b000000??????????0000000000011010 0 0 0 0 1 1 ? ? 0 0 1 0 // DIV
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32'b000000??????????0000000000011011 0 0 0 0 1 1 ? ? 0 0 1 0 // DIVU
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32'b000000???????????????00000100000 0 0 0 1 0 0 1 1 0 0 1 1 // ADD
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32'b000000???????????????00000100000 0 0 0 1 1 1 ? ? 0 0 1 1 // ADD
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32'b000000???????????????00000100001 0 0 0 0 0 0 1 1 0 0 1 1 // ADDU
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32'b000000???????????????00000100010 0 0 0 1 0 0 1 1 0 0 1 1 // SUB
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32'b000000???????????????00000100010 0 0 0 1 1 1 ? ? 0 0 1 1 // SUB
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32'b000000???????????????00000100011 0 0 0 0 0 0 1 1 0 0 1 1 // SUBU
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32'b000000???????????????00000100100 0 0 0 0 0 0 1 1 0 0 1 1 // AND
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32'b000000???????????????00000100101 0 0 0 0 0 0 1 1 0 0 1 1 // OR
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@ -52,7 +52,7 @@
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32'b000101?????????????????????????? 0 0 0 0 0 0 0 0 1 1 1 1 // BNE
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32'b000110?????00000???????????????? 0 0 0 0 0 0 0 0 1 0 1 1 // BLEZ
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32'b000111?????00000???????????????? 0 0 0 0 0 0 0 0 1 0 1 1 // BGTZ
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32'b001000?????????????????????????? 0 0 0 1 0 0 1 0 0 0 1 1 // ADDI
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32'b001000?????????????????????????? 0 0 0 1 1 0 ? 0 0 0 1 1 // ADDI
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32'b001001?????????????????????????? 0 0 0 0 0 0 1 0 0 0 1 1 // ADDIU
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32'b001010?????????????????????????? 0 0 0 0 0 0 1 0 0 0 1 1 // SLTI
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32'b001011?????????????????????????? 0 0 0 0 0 0 1 0 0 0 1 1 // SLTIU
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