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Author SHA1 Message Date
Paul Pan
f8f732bb70 update 
Co-authored-by: Hooo1941 <Hooo1941@users.noreply.github.com>
Co-authored-by: cxy004 <cxy004@qq.com>
 2021-08-15 11:25:08 +08:00
Paul Pan
997f34c7e7 ebase 2021-08-14 21:24:07 +08:00
Paul Pan
cbf99e1b33 tlb entries 32 -> 4 
Co-authored-by: cxy004 <cxy004@qq.com>
Co-authored-by: Hooo1941 <Hooo1941@users.noreply.github.com>
 2021-08-14 20:28:23 +08:00
Paul Pan
4a610a5093 update datapath 2021-08-14 20:19:01 +08:00
Paul Pan
cc81a4f3e4 soft update 2021-08-14 20:18:43 +08:00
Paul Pan
09e0644f08 try tlb optimize 
Co-authored-by: cxy004 <cxy004@qq.com>
Co-authored-by: Hooo1941 <Hooo1941@users.noreply.github.com>
 2021-08-13 22:47:58 +08:00
Paul Pan
eab17474ff add dev lib 2021-08-13 20:40:53 +08:00
Paul Pan
6fe89863b0 1. tlb test PASS 
2. testbench.sv

Co-authored-by: cxy004 <cxy004@qq.com>
 2021-08-13 18:28:04 +08:00
Paul Pan
638a4e60b1 fix mmu 
Co-authored-by: cxy004 <cxy004@qq.com>
Co-authored-by: Hooo1941 <Hooo1941@users.noreply.github.com>
 2021-08-13 13:16:32 +08:00
Paul Pan
27bda939f6 Merge branch 'master' of https://git.builds.ninja/NSCSCC/MIPS 2021-08-12 23:03:34 +08:00
Paul Pan
28752ef2f7 1. AXI add arsize control 
2. MMU & Cache fix bug (cached ff)

Co-authored-by: cxy004 <cxy004@qq.com>
 2021-08-12 23:03:29 +08:00
cxy004
9ac9b951fa decode tools 2021-08-12 21:40:52 +08:00
Paul Pan
22e469ceec 1. tlb: add soft 
2. datapath OFA fix2
3. datapath C0 hazard
4. MMU buffer

Co-authored-by: cxy004 <cxy004@qq.com>
Co-authored-by: Hooo1941 <Hooo1941@users.noreply.github.com>
 2021-08-12 21:38:30 +08:00
Paul Pan
d923ba69c5 datapath fix bug (clear OFA) 
Co-authored-by: cxy004 <cxy004@qq.com>
Co-authored-by: Hooo1941 <Hooo1941@users.noreply.github.com>
 2021-08-11 21:55:54 +08:00
Paul Pan
1153d3aab6 1. MMU fix bug (rvalid) 
2. I/D-Cache refactor

Co-authored-by: cxy004 <cxy004@qq.com>
Co-authored-by: Hooo1941 <Hooo1941@users.noreply.github.com>
 2021-08-11 20:39:24 +08:00
Paul Pan
bc549d8bd4 1. tlb control signals 
2. exccode rename
3. tlb datapath partial

Co-authored-by: cxy004 <cxy004@qq.com>
Co-authored-by: Hooo1941 <Hooo1941@users.noreply.github.com>
 2021-08-11 12:58:02 +08:00
Paul Pan
934a978aa7 update README 2021-08-11 09:27:35 +08:00
Paul Pan
578ef59555 1. tlb cp0 rw 
2. MyCPU top
3. Regfile delete test signals
4. MMU tlb exception signals
5. tlb reset
 2021-08-10 22:47:18 +08:00
Paul Pan
94e9b7bcbd tlb mmu with cache 
simplify AXI
 2021-08-10 21:34:12 +08:00
Paul Pan
a83967f9b9 TLB main 
Co-authored-by: Hooo1941 <Hooo1941@users.noreply.github.com>
Co-authored-by: cxy004 <cxy004@qq.com>
 2021-08-10 20:19:11 +08:00
Paul Pan
50b5a2ae04 TLB init 
Co-authored-by: Hooo1941 <Hooo1941@users.noreply.github.com>
 2021-08-09 23:26:49 +08:00
Paul Pan
24e13ae6c3 fix define 2021-08-08 20:39:26 +08:00
cxy004
5a9e2820a8 try dcache rst 2021-08-08 20:16:11 +08:00
Paul Pan
dccb3f5b8d fix registerfile en 2021-08-08 14:31:11 +08:00
Paul Pan
9be3f3697e fix gen 2021-08-05 18:23:21 +08:00
cxy004
2fd973d877 gen test 2021-08-05 18:22:15 +08:00
cxy004
1cad3f1d8c test genvar & LRU update 2021-08-05 18:12:13 +08:00
cxy004
39d5490971 try pcs 2021-08-05 00:24:31 +08:00
Paul Pan
cac2aad5f1 fix 2021-08-04 23:46:30 +08:00
Paul Pan
d97800ce76 fix 2021-08-04 23:36:59 +08:00
cxy004
834769dd98 mem write forward & LRU fix 2021-08-04 23:33:07 +08:00
cxy004
b2f32735d0 mul support 2021-08-04 11:35:21 +08:00
Paul Pan
fd36f80bd6 BIG: fix dcache & fix HLS!!! 2021-08-03 22:55:21 +08:00
Paul Pan
609908595f overflow success (& alu) 2021-08-03 18:55:14 +08:00
Paul Pan
09b949922a fix def 2021-08-03 17:05:37 +08:00
cxy004
b6b0f840f3 overflow experiment 2021-08-03 16:14:56 +08:00
Paul Pan
6b32775ada add system test 2021-08-03 15:30:27 +08:00
Paul Pan
86b6dc7a3d fix perf tb 2021-08-03 15:28:11 +08:00
Paul Pan
2201513f50 cache update 2021-08-03 14:12:17 +08:00
Paul Pan
b0ace9d98d cp0 minimize 
Co-authored-by: Hooo1941 <Hooo1941@users.noreply.github.com>
 2021-08-03 11:55:25 +08:00
Paul Pan
e62dd7676d fix dcache 2021-08-02 23:49:34 +08:00
Paul Pan
fa89b358df cp0 kseg0 -> cached 2021-08-02 22:26:16 +08:00
Paul Pan
648adced91 Revert "test improve" 
This reverts commit 3d97345460.
 2021-08-02 22:24:59 +08:00
Paul Pan
3d97345460 test improve 2021-08-02 21:42:49 +08:00
Paul Pan
08df1e277f fix ip 2021-08-02 17:43:02 +08:00
cxy004
1889c361a4 Merge remote-tracking branch 'origin/master' 2021-08-02 17:16:47 +08:00
cxy004
b4760f89fd HLS fix 2021-08-02 17:16:34 +08:00
Paul Pan
55965e93e4 update ip 2021-08-02 00:11:21 +08:00
cxy004
3c5c9724bb muldiv fix 2021-08-01 23:41:08 +08:00
Paul Pan
f137fd434f fix? 
fix typo

fix mult
 2021-08-01 22:42:16 +08:00