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Paul Pan 22e469ceec 1. tlb: add soft 2. datapath OFA fix2 3. datapath C0 hazard 4. MMU buffer Co-authored-by: cxy004 <cxy004@qq.com> Co-authored-by: Hooo1941 <Hooo1941@users.noreply.github.com>		2021-08-12 21:38:30 +08:00
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README.md	update README	2021-08-11 09:27:35 +08:00

README.md

Magically Improved Pipeline Stages

Our awesome MIPS CPU written in SystemVerilog for Loongson Cup

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├── resources                <-- 资源包
│   └── 2021                 <-- 2021年资源包
│       ├── cpu132_gettrace  <-- 性能测试基准(gs132)
│       ├── soc_axi_func     <-- AXI功能测试
│       ├── soc_axi_perf     <-- AXI性能测试
│       ├── soc_axi_system   <-- AXI系统测试
│       └── soft             <-- 测试用程序
│           ├── func         <-- 功能测试
│           ├── memory_game  <-- 记忆游戏
│           └── perf_func    <-- 性能测试
├── src                      <-- CPU设计代码
│   ├── AXI                  <-- AXI总线交互
│   ├── Cache                <-- Cache
│   ├── Core                 <-- CPU核心
│   ├── CP0                  <-- CP0协处理器
│   ├── include              <-- 头文件
│   ├── IP                   <-- 用到的IP
│   ├── MMU                  <-- 地址转换单元
│   └── testbench            <-- 测试脚本
└── tools                    <-- controller生成器