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1. MMU fix bug (rvalid)

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2. I/D-Cache refactor

Co-authored-by: cxy004 <cxy004@qq.com>
Co-authored-by: Hooo1941 <Hooo1941@users.noreply.github.com>
This commit is contained in:
Paul Pan 2021-08-11 20:39:24 +08:00
parent bc549d8bd4
commit 1153d3aab6
5 changed files with 68 additions and 39 deletions
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52
src/Cache/DCache.sv
View File

@ -45,7 +45,7 @@ module DCache (
logic [3:0] wen;
logic [3:0] wen2;
logic en1, en2; // en1: Lookup->Lookup, en2: Lookup->Rep
logic en2; // en2: Lookup->Rep
DCIndexL_t baddr;
logic bwe1, bwe2; // bwe1: Lookup -> Write, bwe2: Replace -> Lookup
@ -59,7 +59,7 @@ module DCache (
ffen #(`DC_TAGL-`DC_INDEXL) index_ff (
clk,
port.index,
en1,
port.req,
index1
);
ffen #(4) wen_ff (
@ -73,36 +73,52 @@ module DCache (
// ======== State Machine ========
// ===============================
enum bit { LOOKUP, REPLACE } state, nextState;
enum bit [1:0] { IDLE, LOOKUP, REPLACE } state, nextState;
always_ff @(posedge clk) begin
if (rst) state <= LOOKUP;
if (rst) state <= IDLE;
else state <= nextState;
end
always_comb begin
en1 = 1'b0;
en2 = 1'b0;
bwe1 = 1'b0; // Lookup -> Write
bwe2 = 1'b0; // Replace -> Lookup
nextState = state;
case (state)
IDLE: begin
if (port.req) begin
nextState = LOOKUP;
end
end
LOOKUP: begin
if (~port.valid | hit) begin // hit
if (port.wvalid) begin // write
bwe1 = 1'b1;
end else begin // read
en1 = 1'b1;
if (~port.valid) begin
if (~port.req) begin
nextState = IDLE;
end
end else begin
if (hit) begin
if (port.wvalid) begin
bwe1 = 1'b1;
end else begin
if (~port.req) begin
nextState = IDLE;
end
end
end else begin
en2 = 1'b1;
nextState = REPLACE;
end
end else begin // ~hit
en2 = 1'b1;
nextState = REPLACE;
end
end
REPLACE: begin
if (port.rvalid) begin
bwe2 = 1'b1;
nextState = LOOKUP;
if (port.req) begin
nextState = LOOKUP;
end else begin
nextState = IDLE;
end
end
end
endcase
@ -189,10 +205,10 @@ module DCache (
for (integer i = 0; i < 128; i++)
LRU[i] <= 4'b0;
end else begin
if (en1) begin
nowLRU <= LRU[port.index];
if (port.req) begin
if (port.valid)
LRU[index1] <= nextLRU;
LRU[index1] = nextLRU;
nowLRU = LRU[port.index];
end
end
end
@ -204,7 +220,7 @@ module DCache (
mux2 #(`DC_TAGL-`DC_INDEXL) index_mux (
index1,
port.index,
en1,
port.req,
baddr
);

35
src/Cache/ICache.sv
View File

@ -35,7 +35,7 @@ module ICache (
logic [3:0] wen;
logic [3:0] wen2;
logic en1, en2; // en1: Lookup->Lookup, en2: Lookup->Rep
logic en2; // en2: Lookup->Rep
ICIndexL_t baddr;
logic bwe;
@ -44,28 +44,34 @@ module ICache (
// ======== Flip-Flop ========
// ===========================
ffen#(`IC_TAGL-`IC_INDEXL) index_ff(clk, port.index, en1, index1);
ffen#(`IC_TAGL-`IC_INDEXL) index_ff(clk, port.index, port.req, index1);
ffen#(4) wen_ff(clk, wen, en2, wen2);
// ===============================
// ======== State Machine ========
// ===============================
enum bit { LOOKUP, REPLACE } state, nextState;
enum bit [1:0] { IDLE, LOOKUP, REPLACE } state, nextState;
always_ff @(posedge clk) begin
if(rst) state <= LOOKUP;
if(rst) state <= IDLE;
else state <= nextState;
end
always_comb begin
en1 = 1'b0;
en2 = 1'b0;
nextState = state;
case (state)
IDLE: begin
if (port.req) begin
nextState = LOOKUP;
end
end
LOOKUP: begin
if (~port.valid | hit) begin
en1 = 1'b1;
if (~port.req) begin
nextState = IDLE;
end
end else begin
en2 = 1'b1;
nextState = REPLACE;
@ -73,7 +79,11 @@ module ICache (
end
REPLACE: begin
if (port.rvalid) begin
nextState = LOOKUP;
if (port.req) begin
nextState = LOOKUP;
end else begin
nextState = IDLE;
end
end
end
endcase
@ -141,10 +151,10 @@ module ICache (
initial LRU[i] = 4'b0;
always_ff @(posedge clk) begin
if (en1) begin
nowLRU <= LRU[port.index];
if (port.req) begin
if (port.valid)
LRU[index1] <= nextLRU;
LRU[index1] = nextLRU;
nowLRU = LRU[port.index];
end
end
@ -155,7 +165,7 @@ module ICache (
mux2 #(`IC_TAGL-`IC_INDEXL) index_mux (
index1,
port.index,
en1,
port.req,
baddr
);
assign bwe = (state == REPLACE) & port.rvalid;
@ -247,4 +257,3 @@ module ICache (
);
endmodule

10
src/MMU/MMU.sv
View File

@ -218,10 +218,11 @@ module MMU (
{inst.rdata1, inst.rdata0}
);
assign ic.req = iEn;
assign ic.valid = iReq1 & iCached1;
assign ic.index = iVA[`IC_TAGL-1:`IC_INDEXL];
assign ic.tag1 = iPA1[31:`IC_TAGL];
assign ic.rvalid = inst_axi.data_ok;
assign ic.rvalid = inst_axi.rvalid & inst_axi.data_ok;
mux4 #(256) ic_rdata_mux (
{inst_axi.rdata, iD7, iD6, iD5, iD4, iD3, iD2, iD1},
@ -299,7 +300,7 @@ module MMU (
// ================================
assign dVA = data.addr;
assign dValid1 = dReq1 & dHit1 & dMValid1;
assign dValid1 = dReq1 & dHit1 & dMValid1 & (~dwr1 | ~dDirty1);
assign dTLBRefill = dReq1 & ~dHit1;
assign dTLBInvalid = dReq1 & ~dMValid1;
@ -334,7 +335,7 @@ module MMU (
rdata_axi.req = 0;
case (drState)
DR_IDLE: begin
if (~dValid1 | dDirty1) dEn = 1;
if (~dValid1) dEn = 1;
else begin
dwEn = 1;
if (data.wr) data.data_ok = 1;
@ -429,11 +430,12 @@ module MMU (
data.rdata
);
assign dc.req = dEn;
assign dc.valid = dValid1 & dCached1;
assign dc.index = dVA[`DC_TAGL-1:`DC_INDEXL];
assign dc.tag1 = dPA1[31:`DC_TAGL];
assign dc.sel1 = dPA1[3:2];
assign dc.rvalid = rdata_axi.data_ok;
assign dc.rvalid = rdata_axi.rvalid & rdata_axi.data_ok;
mux4 #(128) dc_rdata_mux (
{rdata_axi.rdata, drD3, drD2, drD1},
{drD3, drD2, drD1, rdata_axi.rdata},

5
src/include/DCache.svh
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@ -34,6 +34,7 @@ typedef struct packed {
} DCDataRAM_t;
interface DCache_i;
logic req;
logic valid;
DCIndexL_t index;
DCTagL_t tag1;
@ -50,13 +51,13 @@ interface DCache_i;
DCData_t row;
modport cache(
input valid,
input req, valid,
input index, tag1, sel1,
input rvalid, rdata, wvalid, wdata, wstrb,
output hit, dirt_valid, dirt_addr, dirt_data, row
);
modport mmu(
output valid,
output req, valid,
output index, tag1, sel1,
output rvalid, rdata, wvalid, wdata, wstrb,
input hit, dirt_valid, dirt_addr, dirt_data, row

5
src/include/ICache.svh
View File

@ -33,6 +33,7 @@ typedef struct packed {
} ICDataRAM_t;
interface ICache_i;
logic req;
logic valid;
ICIndexL_t index;
ICTagL_t tag1;
@ -41,11 +42,11 @@ interface ICache_i;
logic rvalid;
ICData_t rdata;
modport cache(input valid,
modport cache(input req, valid,
input index, tag1,
output hit, row,
input rvalid, rdata);
modport mmu(output valid,
modport mmu(output req, valid,
output index, tag1,
input hit, row,
output rvalid, rdata);