try pcs
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@ -193,27 +193,26 @@ module DCache (
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// Update LRU
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always_comb begin
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nextLRU = nowLRU;
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if (wen[0]) begin
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if (wen[0])
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casez (nowLRU)
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4'b111?: nextLRU = 4'b0001;
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default: nextLRU[0] = 1'b1;
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endcase
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end else if (wen[1]) begin
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if (wen[1])
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casez (nowLRU)
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4'b11?1: nextLRU = 4'b0010;
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default: nextLRU[1] = 1'b1;
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endcase
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end else if (wen[2]) begin
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if (wen[2])
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casez (nowLRU)
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4'b1?11: nextLRU = 4'b0100;
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default: nextLRU[2] = 1'b1;
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endcase
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end else if (wen[3]) begin
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if (wen[3])
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casez (nowLRU)
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4'b?111: nextLRU = 4'b1000;
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default: nextLRU[3] = 1'b1;
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endcase
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end
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end
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always_ff @(posedge clk) begin
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@ -105,8 +105,6 @@ module ICache (
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assign port.hit = hit;
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assign port.row = cacheLine;
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// assign nowLRU = LRU[index];
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// ==============================
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// ========== Replace ===========
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// ==============================
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@ -28,12 +28,11 @@ module Controller (
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imm
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);
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assign ctrl.PCS = PCS_t'({
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~inst[28] & (inst[27] | ~inst[26]),
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~inst[27] & (~inst[26] & inst[28] & eq | inst[26] & (~inst[28] & (inst[16] & ~ltz | ~inst[16] & ltz) | inst[28] & ~eq)) | inst[27] & (~inst[28] | (~inst[26] & (eq | ltz) | inst[26] & ~eq & ~ltz))
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});
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assign ctrl.BJRJ = ~inst[29] & (~inst[31] & (~inst[30] & ~inst[5] & ~inst[4] & inst[3] & ~inst[2] | inst[28] | inst[26]) | inst[27] & ~inst[26]);
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assign ctrl.B = ~inst[31] & ~inst[29] & (inst[28] | ~inst[27] & inst[26]);
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assign ctrl.JR = ~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & ~inst[5] & ~inst[4] & inst[3] & ~inst[2];
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assign ctrl.J = ~inst[31] & ~inst[29] & ~inst[28] & inst[27];
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assign ctrl.BGO = ~inst[26] & (eq | inst[27] & ltz) | inst[26] & (~inst[27] & (~inst[28] & (inst[16] & ~ltz | ~inst[16] & ltz) | inst[28] & ~eq) | inst[27] & ~eq & ~ltz);
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assign ctrl.SYSCALL = ~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[3] & inst[2] & ~inst[0];
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assign ctrl.BREAK = ~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[3] & inst[2] & inst[0];
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@ -41,7 +40,6 @@ module Controller (
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assign ctrl.OFA = ~inst[31] & ~inst[28] & ~inst[27] & ~inst[26] & (~inst[30] & inst[5] & ~inst[3] & ~inst[2] & ~inst[0] | inst[29]);
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assign ctrl.ES = inst[31] | ~inst[30] & ~inst[28] & ~inst[27] & ~inst[26] & (inst[5] | inst[4] & inst[3] & ~inst[2] | ~inst[3] & inst[2]) | inst[29];;
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// assign ctrl.ET = ~inst[26] & ~inst[27] & (~inst[30] & ~inst[28] & (~inst[31] & ~inst[29] & (inst[5] | (~inst[1] & (~inst[4] & ~inst[3] & ~inst[0] | inst[4] & inst[3]) | inst[1] & (~inst[4] | inst[3]))) | inst[31] & inst[29]) | inst[30] & inst[29]) | inst[26] & inst[31] & inst[29];
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assign ctrl.ET = ~inst[31] & ~inst[27] & ~inst[26] & (~inst[30] & ~inst[29] & ~inst[28] & (inst[5] | (~inst[1] & (~inst[4] & ~inst[3] & ~inst[0] | inst[4] & inst[3]) | inst[1] & (~inst[4] | inst[3]))) | inst[30] & inst[29]);
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assign ctrl.DS = ~inst[31] & ~inst[29] & (inst[28] | ~inst[27] & (~inst[30] & ~inst[5] & ~inst[4] & inst[3] & ~inst[2] | inst[26]));
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assign ctrl.DT = ~inst[31] & ~inst[29] & inst[28] & ~inst[27];
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@ -54,9 +54,6 @@ module Datapath (
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word_t PF_pcjr;
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word_t PF_pc0;
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// F
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logic F_valid;
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// Instr Queue
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logic IQ_IA_valid;
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word_t IQ_IA_inst;
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@ -232,30 +229,22 @@ module Datapath (
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assign PF_pcb = {D.IB_pc[31:2] + {{14{D.IA_inst[15]}}, D.IA_inst[15:0]}, 2'b0};
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assign PF_pcjr = D_IA_ForwardS;
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assign PF_pcj = {D.IB_pc[31:28], D.IA_inst[25:0], 2'b0};
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mux4 #(32) PF_pc0_mux (
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PF_pcp8,
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PF_pcb,
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PF_pcjr,
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PF_pcj,
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D.IA.PCS,
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PF_pc0
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);
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prio_mux5 #(32) PF_pc_mux (
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assign PF_pc0 = {32{D.IA.B}} & PF_pcb | {32{D.IA.JR}} & PF_pcjr | {32{D.IA.J}} & PF_pcj;
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prio_mux4 #(32) PF_pc_mux (
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PF_pc0,
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PF_pcp8,
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`PCEXC,
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C0_EPC,
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`PCRST,
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{~F_valid, M_exception.ERET, M_exception.ExcValid, ~D_IB_valid | ~D.IA.BJRJ},
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{M_exception.ERET, M_exception.ExcValid, ~D_IB_valid | ~D.IA.BJRJ | D.IA.B & ~D.IA.BGO},
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PF.pc
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);
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assign rstD = D_IA_valid & D.IA.BJRJ & D.IA.PCS != PCP8 & D_IB_valid & D_readygo;
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assign rstD = D_IA_valid & (D.IA.B & D.IA.BGO | D.IA.JR | D.IA.J) & D_IB_valid & D_readygo;
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assign rstM = C0_exception.ExcValid;
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assign PF_go = ~D.IA_ExcValid & ~D.IB_ExcValid & ~E_I0_ExcValidWithoutOF & ~E_I1_ExcValidWithoutOF
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& (~D_IB_valid | ~D.IA.JR | PF_pcjr[1:0] == 2'b00);
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assign fetch_i.req = ~F_valid | M_exception.ExcValid
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assign fetch_i.req = M_exception.ExcValid
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| PF_go & (~D_IB_valid & ~IQ_valids[0] | (~D.IA.BJRJ | D_readygo)
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& (rstD
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| ~IQ_valids[0]
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@ -270,14 +259,7 @@ module Datapath (
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//---------------------------------------------------------------------------//
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// F.FF
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ffenr #(1) F_valid_ff (
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clk, rst,
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1'b1,
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1'b1,
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F_valid
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);
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ffenr #(32) F_pc_ff (
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pcenr F_pc_ff (
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clk,
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rst,
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PF.pc,
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@ -451,7 +433,7 @@ module Datapath (
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assign D.en0 = ~D_IA_valid | ~D_IB_valid | D_go & E.en;
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assign D.en1 = ~D_IA_valid | D_IB_can_dispatch & D_go & E.en;
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assign D_go = (~PF_go | ~D.IA.BJRJ | D.IA.PCS == PCP8 | fetch_i.req & fetch_i.addr_ok) & D_IA_can_dispatch | D.IA_ExcValid;
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assign D_go = (~PF_go | ~D.IA.BJRJ | D.IA.B & ~D.IA.BGO| fetch_i.req & fetch_i.addr_ok) & D_IA_can_dispatch | D.IA_ExcValid;
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assign D_IA_go = D_IA_valid & ~D.IA_ExcValid;
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assign D_IB_go = D_IB_valid & ~D.IB_ExcValid & D_IB_can_dispatch & ~D.IA_ExcValid;
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@ -1,15 +1,14 @@
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`include "defines.svh"
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module pcenr (
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input clk,
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rst,
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input clk, rst,
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input word_t d,
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input logic en,
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output word_t q
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);
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always_ff @(posedge clk)
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if (rst) q <= 32'b0;
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if (rst) q <= (`PCRST - 8);
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else if (en) q <= d;
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endmodule
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@ -38,13 +38,6 @@ typedef struct packed {
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logic alt;
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} aluctrl_t;
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typedef enum logic [1:0] {
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PCP8 = 2'b00,
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B = 2'b01,
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JR = 2'b10,
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J = 2'b11
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} PCS_t;
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typedef enum logic [1:0] {
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SA = 2'b00,
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PC = 2'b01,
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@ -109,9 +102,11 @@ typedef struct packed {
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logic [4:0] RS;
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logic [4:0] RT;
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PCS_t PCS;
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logic BJRJ;
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logic B;
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logic JR;
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logic J;
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logic BGO;
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logic DP0;
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logic DP1;
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logic DS;
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