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7b33e4213a
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a big update
1. add test soft
2. modify verilator (TODO: crossbar need to replace)
3. fix CP0: now CU0 is always 1
4. Controller: cacheop
5. Controller: fix TEN
6. mycpu_top fix CP0_i
7. fix AXI.sv
8. fix AXIReader.sv
9. fix AXIWriter.sv: getting the correct data and length
10. MU: fix cache writeback, fix mem data mux, fix writer address, fix read request
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2022-07-29 18:25:58 +08:00 |
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9ce588757d
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feat: MU rewrite 1
1. ALU format
2. FIX hazard (MOVN / MOVZ)
3. verilator support
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2022-07-27 15:07:16 +08:00 |
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75a62cfc37
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try add trap
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2021-09-22 13:41:09 +08:00 |
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29c6e16682
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try add MOVZ, MOVN
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2021-09-07 19:24:34 +08:00 |
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1f2d7f6f3c
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1. fix deadlock on continuous CACHE inst
2. enhance the testcases
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2021-09-04 21:07:00 +08:00 |
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17f64e1f2f
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1. add cache (D-Cache Address) inst
2. fix bug in ALR
3. fix bug in MMU and DCache
4. Register File rst
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2021-09-02 19:20:19 +08:00 |
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f256abd248
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add control signals
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2021-09-02 19:05:23 +08:00 |
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53c0c018bb
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fix bug in decode
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2021-08-31 21:11:59 +08:00 |
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966b7b6223
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add control signals
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2021-08-31 18:30:03 +08:00 |
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0b872c9b7c
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add sync pref as nop
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2021-08-30 13:11:40 +08:00 |
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eea7b6bbda
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add lwl lwr swl swr test cases
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2021-08-29 20:17:42 +08:00 |
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1f94aebd9d
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update control signals for swl/swr
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2021-08-29 16:47:34 +08:00 |
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54c6794a77
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add LWL and LWR
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2021-08-26 18:32:55 +08:00 |
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1ad35234dc
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txt add tlbwr
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2021-08-26 17:04:09 +08:00 |
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8d039f4327
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handle CpU exception
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2021-08-25 20:59:32 +08:00 |
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ba546d1d5f
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add tlbwr datapath
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2021-08-24 16:23:57 +08:00 |
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cxy004
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67ccb57eda
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RW & RS0 fix
tools update
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2021-08-18 12:16:28 +08:00 |
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cxy004
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9ac9b951fa
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decode tools
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2021-08-12 21:40:52 +08:00 |
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22e469ceec
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1. tlb: add soft
2. datapath OFA fix2
3. datapath C0 hazard
4. MMU buffer
Co-authored-by: cxy004 <cxy004@qq.com>
Co-authored-by: Hooo1941 <Hooo1941@users.noreply.github.com>
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2021-08-12 21:38:30 +08:00 |
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bc549d8bd4
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1. tlb control signals
2. exccode rename
3. tlb datapath partial
Co-authored-by: cxy004 <cxy004@qq.com>
Co-authored-by: Hooo1941 <Hooo1941@users.noreply.github.com>
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2021-08-11 12:58:02 +08:00 |
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fd36f80bd6
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BIG: fix dcache & fix HLS!!!
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2021-08-03 22:55:21 +08:00 |
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Hooo1941
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e7650b40a0
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Create iq.sv
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2021-08-01 19:26:04 +08:00 |
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cxy004
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8002b8c56a
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simplify
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2021-08-01 15:46:53 +08:00 |
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a0a6e4c2f2
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fix5
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2021-07-30 21:51:20 +08:00 |
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cxy004
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99436d9a42
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fix3
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2021-07-30 03:31:42 +08:00 |
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5f8e8a8c6a
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fix2
Co-authored-by: cxy004 <cxy004@qq.com>
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2021-07-29 22:54:45 +08:00 |
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ebcd281f4b
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datapath
Co-authored-by: cxy004 <cxy004@qq.com>
Co-authored-by: Hooo1941 <Hooo1941@users.noreply.github.com>
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2021-07-28 16:39:10 +08:00 |
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906eb052fa
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control signal
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2021-07-27 22:23:03 +08:00 |
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d2b4570c9e
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controller + prefetch + iq
Co-authored-by: Hooo1941 <Hooo1941@users.noreply.github.com>
Co-authored-by: cxy004 <cxy004@qq.com>
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2021-07-26 22:29:59 +08:00 |
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hoo
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880bebb97b
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Big Update
Co-authored-by: Paul <1323564116@qq.com>
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2021-07-15 17:39:24 +08:00 |
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cxy004
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4abcd625cf
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datapath wip
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2021-07-07 23:06:42 +08:00 |
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Hooo1941
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d0839f6423
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instrqueue
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2021-07-07 16:55:10 +08:00 |
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cxy004
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9113c47b74
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ctrl maker
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2021-07-07 13:32:23 +08:00 |
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cxy004
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304ae7f8ce
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ctrl tools & gadgets & interfaces
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2021-07-05 15:25:15 +08:00 |
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