instrqueue
This commit is contained in:
parent
9113c47b74
commit
d0839f6423
164
src/Core/InstrQueue.sv
Normal file
164
src/Core/InstrQueue.sv
Normal file
@ -0,0 +1,164 @@
|
||||
`include "defines.svh"
|
||||
|
||||
module InstrQueue (
|
||||
input logic clk,
|
||||
input logic rst,
|
||||
HandShake.prev HandShake_in1,
|
||||
input word_t in1,
|
||||
HandShake.prev HandShake_in2,
|
||||
input word_t in2,
|
||||
HandShake.next HandShake_out1,
|
||||
output word_t out1,
|
||||
HandShake.next HandShake_out2,
|
||||
output word_t out2
|
||||
);
|
||||
|
||||
/*
|
||||
instr: ffen
|
||||
valid: ffenr
|
||||
readygo to valid
|
||||
0:
|
||||
0out: instr1<-in1, instr2<-in2
|
||||
1out: out1<-in1, instr1<-in2
|
||||
2out: out1<-in1, out2<-in2
|
||||
1:
|
||||
0out: instr2<-in1, instr3<-in2
|
||||
1out: out1<-instr1 instr1<-in1 instr2<-in2
|
||||
2out: out1<-instr1 out2<-in1 instr1<-in2
|
||||
2:
|
||||
0out: instr4<-in1
|
||||
1out: out1<-instr1 instr1<-instr2 instr2<-in1 instr3<-in2
|
||||
2out: out1<-instr1 out2<-instr2 instr1<-in1 instr2<-in2
|
||||
3:
|
||||
1out: out1<-instr1 instr1<-instr2 instr2<-in1 instr3<-in2
|
||||
2out: out1<-instr1 out2<-instr2 instr1<-instr3 instr2<-in1 instr3<-in2
|
||||
4:
|
||||
0out:
|
||||
1out: out1<-instr1 instr1<-instr2 instr2<-instr3 instr3<-in1
|
||||
2out: out1<-instr1 out2<-instr2 instr1<-instr3 instr3<-instr4 instr4<-in1
|
||||
|
||||
无直通
|
||||
0:
|
||||
0out: instr1<-in1, instr2<-in2
|
||||
1out: instr1<-in1, instr2<-in2
|
||||
2out: instr1<-in1, instr2<-in2
|
||||
1:
|
||||
0out: instr2<-in1, instr3<-in2
|
||||
1out: out1<-instr1 instr1<-in1 instr2<-in2
|
||||
2out: out1<-instr1 instr1<-in1 instr2<-in2
|
||||
2:
|
||||
0out: instr3<-in1 instr4<-in2
|
||||
1out: out1<-instr1 instr1<-instr2 instr2<-in1 instr3<-in2
|
||||
2out: out1<-instr1 out2<-instr2 instr1<-in1 instr2<-in2
|
||||
3:
|
||||
0out: instr4<-in1
|
||||
1out: out1<-instr1 instr1<-instr2 instr2<-instr3 instr3<-in1 instr4<-in2
|
||||
2out: out1<-instr1 out2<-instr2 instr1<-instr3 instr2<-in1 instr3<-in2
|
||||
4:
|
||||
0out: nop
|
||||
1out: out1<-instr1 instr1<-instr2 instr2<-instr3 instr3<-instr4 instr4<-in1
|
||||
2out: out1<-instr1 out2<-instr2 instr1<-instr3 instr2<-instr4 instr3<-in1 instr4<-in2
|
||||
*/
|
||||
|
||||
parameter DEPTH = 2, MAX_COUNT = 2'b11;
|
||||
word_t di1, di2, di3, di4, qi1, qi2, qi3, qi4;
|
||||
logic en1, en2, en3, en4;
|
||||
logic dv1, dv2, dv3, dv4, qv1, qv2, qv3, qv4;
|
||||
ffen #(32) instr1 (
|
||||
clk,
|
||||
di1,
|
||||
en1,
|
||||
qi1
|
||||
);
|
||||
ffen #(32) instr2 (
|
||||
clk,
|
||||
di2,
|
||||
en2,
|
||||
qi2
|
||||
);
|
||||
ffen #(32) instr3 (
|
||||
clk,
|
||||
di3,
|
||||
en3,
|
||||
qi3
|
||||
);
|
||||
ffen #(32) instr4 (
|
||||
clk,
|
||||
di4,
|
||||
en4,
|
||||
qi4
|
||||
);
|
||||
ffenr #(1) valid1 (
|
||||
clk,
|
||||
rst,
|
||||
dv1,
|
||||
en1,
|
||||
qv1
|
||||
);
|
||||
ffenr #(1) valid2 (
|
||||
clk,
|
||||
rst,
|
||||
dv2,
|
||||
en2,
|
||||
qv2
|
||||
);
|
||||
ffenr #(1) valid3 (
|
||||
clk,
|
||||
rst,
|
||||
dv3,
|
||||
en3,
|
||||
qv3
|
||||
);
|
||||
ffenr #(1) valid4 (
|
||||
clk,
|
||||
rst,
|
||||
dv4,
|
||||
en4,
|
||||
qv4
|
||||
);
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (rst) begin
|
||||
out1.v = 1'b0;
|
||||
out2.v = 1'b0;
|
||||
end
|
||||
end
|
||||
logic [5:0] judge = {qv4, qv3, qv2, qv1, HandShake_out1.allowin, HandShake_out2.allowin};
|
||||
assign HandShake_out1.readygo = judge[1] & judge[2];
|
||||
assign HandShake_out1.readygo = judge[0] & judge[3];
|
||||
assign out1 = qi1;
|
||||
assign out2 = qi2;
|
||||
assign HandShake_in1.allowin = ~judge[5] | judge[1];
|
||||
assign HandShake_in2.allowin = (~judge[4] | judge[1] & (~judge[5] | judge[0]));
|
||||
assign en1 = ~judge[2] | judge[1];
|
||||
assign en2 = ~judge[3] | judge[1];
|
||||
assign en3 = (~judge[3] & ~judge[1] & judge[2] | judge[3] & (~judge[1] & ~judge[4] | judge[1] & (~judge[4] & ~judge[0] | judge[4])));
|
||||
assign en4 = (~judge[4] & judge[3] & ~judge[1] | judge[4] & (~judge[1] & ~judge[5] | judge[1] & (~judge[5] & ~judge[0] | judge[5])));
|
||||
assign dv1 = HandShake_in1.readygo;
|
||||
assign dv2 = HandShake_in2.readygo;
|
||||
assign dv3 = HandShake_in3.readygo;
|
||||
assign dv4 = HandShake_in4.readygo;
|
||||
mux3 #(32) mux3_di1 (
|
||||
in1,
|
||||
qi3,
|
||||
qi2,
|
||||
(judge[3] & ~judge[0]) ? 2'b10 : ((judge[3] & judge[0] & judge[4]) ? 2'b01 : 2'b00),
|
||||
di1
|
||||
);
|
||||
mux4 #(32) mux4_di2 (
|
||||
in2,
|
||||
in1,
|
||||
qi4,
|
||||
qi3,
|
||||
(judge[4] & ~judge[0]) ? 2'b11 : ((judge[4] & judge[0] & judge[5]) ? 2'b10 : ((~judge[4] & (~judge[2] & (~judge[3] & judge[1] | judge[0]))) ? 2'b00 : 2'b01)),
|
||||
di2
|
||||
);
|
||||
mux3 #(32) mux3_di3 (
|
||||
in1,
|
||||
in2,
|
||||
qi4,
|
||||
(judge[5] & ~judge[0]) ? 2'b10 : ((~judge[5] & (~judge[3] | ~judge[4] & judge[1] | judge[0])) ? 2'b01 : 2'b00),
|
||||
di3
|
||||
);
|
||||
assign di4 = (judge[4] & ~judge[0] & (~judge[1] | judge[5])) ? in1 : in2;
|
||||
endmodule
|
@ -5,11 +5,6 @@ typedef logic [31:0] word_t;
|
||||
typedef logic [15:0] hfwd_t;
|
||||
typedef logic [7:0] byte_t;
|
||||
|
||||
typedef struct packed {
|
||||
logic v; // readygo
|
||||
logic [31:0] i;
|
||||
} instr;
|
||||
|
||||
typedef struct packed {
|
||||
logic f_sl;
|
||||
logic f_sr;
|
||||
|
82
src/testbench/instrqueue/testbench.sv
Normal file
82
src/testbench/instrqueue/testbench.sv
Normal file
@ -0,0 +1,82 @@
|
||||
`include "defines.svh"
|
||||
|
||||
module testbench();
|
||||
word_t a, b;
|
||||
aluctrl_t aluctrl;
|
||||
word_t aluout;
|
||||
logic overflow;
|
||||
|
||||
alu alu(
|
||||
a, b,
|
||||
aluctrl,
|
||||
aluout,
|
||||
overflow);
|
||||
|
||||
initial begin
|
||||
$dumpfile("test.vcd");
|
||||
$dumpvars(0, testbench);
|
||||
end
|
||||
|
||||
always begin
|
||||
a = 32'h00000004; b = 32'hDEADBEEF;
|
||||
aluctrl = 9'b100000000; #50; // SLL
|
||||
aluctrl = 9'b100000001; #50;
|
||||
aluctrl = 9'b010000000; #50; // SRL
|
||||
aluctrl = 9'b010000001; #50; // SRA
|
||||
a = 32'd123; b = 32'd456;
|
||||
aluctrl = 9'b001000000; #50; // ADD
|
||||
aluctrl = 9'b001000001; #50; // SUB
|
||||
a = 32'hFFFFABCD; b = 32'h0000ABCD;
|
||||
aluctrl = 9'b001000000; #50; // ADD
|
||||
aluctrl = 9'b001000001; #50; // SUB
|
||||
a = 32'h80000000; b = 32'h80000000;
|
||||
aluctrl = 9'b001000000; #50; // ADD
|
||||
aluctrl = 9'b001000001; #50; // SUB
|
||||
a = 32'h7FFFABCD; b = 32'h0000ABCD;
|
||||
aluctrl = 9'b001000000; #50; // ADD
|
||||
aluctrl = 9'b001000001; #50; // SUB
|
||||
a = 32'h8000ABCC; b = 32'h0000ABCD;
|
||||
aluctrl = 9'b001000000; #50; // ADD
|
||||
aluctrl = 9'b001000001; #50; // SUB
|
||||
a = 32'h80000000; b = 32'h7FFFFFFF;
|
||||
aluctrl = 9'b001000000; #50; // ADD
|
||||
aluctrl = 9'b001000001; #50; // SUB
|
||||
a = 32'hABCDABCD; b = 32'hFFABAB00;
|
||||
aluctrl = 9'b000100000; #50; // AND
|
||||
aluctrl = 9'b000100001; #50;
|
||||
aluctrl = 9'b000010000; #50; // OR
|
||||
aluctrl = 9'b000010001; #50; // NOR
|
||||
aluctrl = 9'b000001000; #50; // XOR
|
||||
aluctrl = 9'b000001001; #50;
|
||||
a = 32'hDEADBEEF; b = 32'h0000ABCD;
|
||||
aluctrl = 9'b000000101; #50; // SLT
|
||||
a = 32'h0000ABCD; b = 32'hDEADBEEF;
|
||||
aluctrl = 9'b000000101; #50; // SLT
|
||||
a = 32'h0000ABCC; b = 32'h0000ABCD;
|
||||
aluctrl = 9'b000000101; #50; // SLT
|
||||
a = 32'h0000ABCD; b = 32'h0000ABCC;
|
||||
aluctrl = 9'b000000101; #50; // SLT
|
||||
a = 32'hDEADBEEE; b = 32'hDEADBEEF;
|
||||
aluctrl = 9'b000000101; #50; // SLT
|
||||
a = 32'hDEADBEEF; b = 32'hDEADBEEE;
|
||||
aluctrl = 9'b000000101; #50; // SLT
|
||||
a = 32'hDEADBEEF; b = 32'hDEADBEEF;
|
||||
aluctrl = 9'b000000101; #50; // SLT
|
||||
a = 32'hDEADBEEF; b = 32'h0000ABCD;
|
||||
aluctrl = 9'b000000011; #50; // SLTU
|
||||
a = 32'h0000ABCD; b = 32'hDEADBEEF;
|
||||
aluctrl = 9'b000000011; #50; // SLTU
|
||||
a = 32'h0000ABCC; b = 32'h0000ABCD;
|
||||
aluctrl = 9'b000000011; #50; // SLTU
|
||||
a = 32'h0000ABCD; b = 32'h0000ABCC;
|
||||
aluctrl = 9'b000000011; #50; // SLTU
|
||||
a = 32'hDEADBEEE; b = 32'hDEADBEEF;
|
||||
aluctrl = 9'b000000011; #50; // SLTU
|
||||
a = 32'hDEADBEEF; b = 32'hDEADBEEE;
|
||||
aluctrl = 9'b000000011; #50; // SLTU
|
||||
a = 32'hDEADBEEF; b = 32'hDEADBEEF;
|
||||
aluctrl = 9'b000000011; #50; // SLTU
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
@ -1,8 +1,9 @@
|
||||
with open('ctrl.sv') as f:
|
||||
with open('instrqueue.sv') as f:
|
||||
lines = f.readlines()
|
||||
title = lines[0].split()
|
||||
items = [x.split() for x in lines[1:]]
|
||||
|
||||
preq = title[0].count('/')
|
||||
bits = title[0].count('-')
|
||||
|
||||
def gini(d):
|
||||
@ -47,9 +48,9 @@ def solve(d):
|
||||
raise "fuck"
|
||||
s0 = [(k, v) for k, v in d if k[min_idx] == '0']
|
||||
s1 = [(k, v) for k, v in d if k[min_idx] == '1']
|
||||
return union(solve(s0), solve(s1), 31 - min_idx)
|
||||
return union(solve(s0), solve(s1), bits - 1 - min_idx)
|
||||
|
||||
for i in range(1, len(title)):
|
||||
print(title[i])
|
||||
ans = solve([(item[0][4:], item[i]) for item in items if item[i] != '?'])
|
||||
ans = solve([(item[0][preq:], item[i]) for item in items if item[i] != '?'])
|
||||
print(ans)
|
||||
|
16
tools/instrqueue.sv
Normal file
16
tools/instrqueue.sv
Normal file
@ -0,0 +1,16 @@
|
||||
///------ HandShake_out1.readygo HandShake_out2.readygo out1 out2 HandShake_in1.allowin HandShake_in2.allowin en1 en2 en3 en4 di1 di2 di3 di4
|
||||
6'b000000 0 0 qi1 qi2 1 1 1 1 0 0 in1 in2 ? ?
|
||||
6'b000010 0 0 qi1 qi2 1 1 1 1 0 0 in1 in2 ? ?
|
||||
6'b000011 0 0 qi1 qi2 1 1 1 1 0 0 in1 in2 ? ?
|
||||
6'b000100 0 0 qi1 qi2 1 1 0 1 1 0 ? in1 in2 ?
|
||||
6'b000110 1 0 qi1 qi2 1 1 1 1 0 0 in1 in2 ? ?
|
||||
6'b000111 1 0 qi1 qi2 1 1 1 1 0 0 in1 in2 ? ?
|
||||
6'b001100 0 0 qi1 qi2 1 1 0 0 1 1 ? ? in1 in2
|
||||
6'b001110 1 0 qi1 qi2 1 1 1 1 1 0 qi2 in1 in2 ?
|
||||
6'b001111 1 1 qi1 qi2 1 1 1 1 0 0 in1 in2 ? ?
|
||||
6'b011100 0 0 qi1 qi2 1 0 0 0 0 1 ? ? ? in1
|
||||
6'b011110 1 0 qi1 qi2 1 1 1 1 1 1 qi2 qi3 in1 in2
|
||||
6'b011111 1 1 qi1 qi2 1 1 1 1 1 0 qi3 in1 in2 ?
|
||||
6'b111100 0 0 qi1 qi2 0 0 0 0 0 0 ? ? ? ?
|
||||
6'b111110 1 0 qi1 qi2 1 0 1 1 1 1 qi2 qi3 qi4 in1
|
||||
6'b111111 1 1 qi1 qi2 1 1 1 1 1 1 qi3 qi4 in1 in2
|
Loading…
Reference in New Issue
Block a user