simplify
This commit is contained in:
cxy004
parent
6d5685e6a7
commit
8002b8c56a
@ -8,6 +8,9 @@ module Controller (
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output word_t imm,
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output logic [4:0] sa
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);
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assign ctrl.RS = inst[25:21];
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assign ctrl.RT = inst[20:16];
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mux3 #(5) RD_mux (
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inst[15:11],
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5'b11111,
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@ -16,6 +19,7 @@ module Controller (
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ctrl.RD
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);
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assign sa = inst[10:6];
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mux3 #(32) imm_mux (
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{16'b0, inst[15:0]},
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{{16{inst[15]}}, inst[15:0]},
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@ -24,60 +28,50 @@ module Controller (
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imm
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);
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assign sa = inst[10:6];
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assign ctrl.PCS = PCS_t'({
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~inst[28] & (inst[27] | ~inst[26]),
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~inst[27] & (~inst[26] & inst[28] & eq | inst[26] & (~inst[28] & (inst[16] & ~ltz | ~inst[16] & ltz) | inst[28] & ~eq)) | inst[27] & (~inst[28] | (~inst[26] & (eq | ltz) | inst[26] & ~eq & ~ltz))
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});
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assign ctrl.BJRJ = ~inst[29] & (~inst[31] & (~inst[30] & ~inst[5] & ~inst[4] & inst[3] & ~inst[2] | inst[28] | inst[26]) | inst[27] & ~inst[26]);
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assign ctrl.SYSCALL = ~inst[26] & ~inst[29] & ~inst[30] & ~inst[28] & ~inst[31] & ~inst[27] & inst[2] & inst[3] & ~inst[0];
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assign ctrl.BREAK = ~inst[26] & ~inst[29] & ~inst[30] & ~inst[28] & ~inst[31] & ~inst[27] & inst[2] & inst[3] & inst[0];
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assign ctrl.SYSCALL = ~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[3] & inst[2] & ~inst[0];
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assign ctrl.BREAK = ~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[3] & inst[2] & inst[0];
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assign ctrl.ERET = inst[30] & inst[25];
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assign ctrl.OFA = ~inst[26] & (~inst[29] & ~inst[30] & ~inst[28] & ~inst[31] & ~inst[27] & inst[5] & ~inst[0] & ~inst[2] & ~inst[3] | inst[29] & ~inst[28] & ~inst[31] & ~inst[27]);
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assign ctrl.OFA = ~inst[31] & ~inst[28] & ~inst[27] & ~inst[26] & (~inst[30] & inst[5] & ~inst[3] & ~inst[2] & ~inst[0] | inst[29]);
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assign ctrl.RS = inst[25:21];
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assign ctrl.RT = inst[20:16];
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assign ctrl.PFCtrl.PCS = PCS_t'({
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~inst[27] & ~inst[26] & ~inst[28] & ~inst[31] & ~inst[30] & ~inst[29] & inst[3] & ~inst[4] & ~inst[5] | inst[27] & ~inst[28] & ~inst[29] & ~inst[31],
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~inst[26] & (~inst[27] & inst[28] & ~inst[31] & ~inst[29] & eq | inst[27] & ~inst[29] & (~inst[28] | ltz | eq)) | inst[26] & ~inst[29] & ~inst[31] & (~inst[28] & (~ltz & inst[16] | ltz & ~inst[16] | inst[27]) | inst[28] & ~eq & (~inst[27] | ~ltz))});
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assign ctrl.PFCtrl.BJRJ = ~inst[26] & (~inst[27] & (~inst[28] & ~inst[30] & ~inst[31] & ~inst[29] & inst[3] & ~inst[4] & ~inst[5] & ~inst[2] | inst[28] & ~inst[31] & ~inst[29]) | inst[27] & ~inst[29]) | inst[26] & ~inst[29] & ~inst[31];
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assign ctrl.PFCtrl.BJR = ~inst[26] & (~inst[28] & ~inst[30] & ~inst[29] & ~inst[31] & ~inst[27] & inst[3] & ~inst[4] & ~inst[5] & ~inst[2] | inst[28] & ~inst[29] & ~inst[31]) | inst[26] & ~inst[29] & ~inst[31] & (~inst[27] | inst[27] & inst[28]);
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assign ctrl.PFCtrl.BE = inst[28] & ~inst[29] & ~inst[31] & ~inst[27];
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assign ctrl.ES = inst[31] | ~inst[30] & ~inst[28] & ~inst[27] & ~inst[26] & (inst[5] | inst[4] & inst[3] & ~inst[2] | ~inst[3] & inst[2]) | inst[29];;
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assign ctrl.ET = ~inst[28] & (~inst[26] & (~inst[31] & ~inst[29] & (inst[5] | (~inst[1] & (~inst[0] & (~inst[4] & ~inst[3] | inst[4] & inst[3]) | inst[0] & inst[4] & inst[3]) | inst[1] & (~inst[4] | inst[3]))) | inst[31] & inst[29]) & ~inst[30] & ~inst[27] | inst[26] & inst[31] & inst[29]);
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assign ctrl.DS = ~inst[31] & ~inst[29] & (inst[28] | ~inst[27] & (~inst[30] & ~inst[5] & ~inst[4] & inst[3] & ~inst[2] | inst[26]));
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assign ctrl.DT = ~inst[31] & ~inst[29] & inst[28] & ~inst[27];
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assign ctrl.DCtrl.DP0 = ~inst[31];
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assign ctrl.DCtrl.DP1 = ~inst[30] & (~inst[26] & (~inst[29] & (~inst[28] & (~inst[31] & (~inst[27] & ~inst[4] | inst[27]) | inst[31]) | inst[28]) | inst[29]) | inst[26]) | inst[30] & inst[25];
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assign ctrl.DCtrl.DP1 = ~inst[30] & (inst[31] | inst[29] | inst[28] | inst[27] | inst[26] | ~inst[4]) | inst[30] & inst[25];
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assign ctrl.ECtrl.OP.f_sl = ~inst[31] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & ~inst[5] & ~inst[3] & ~inst[1];
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assign ctrl.ECtrl.OP.f_sr = ~inst[31] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & ~inst[5] & inst[1];
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assign ctrl.ECtrl.OP.f_add = inst[31] | ~inst[28] & (~inst[26] & ~inst[27] & (inst[29] | ~inst[5] & inst[3] & ~inst[1] | inst[5] & ~inst[3] & ~inst[2]) | inst[26] & (~inst[29] | ~inst[27]));
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assign ctrl.ECtrl.OP.f_and = ~inst[31] & (~inst[28] & ~inst[29] & ~inst[27] & ~inst[26] & inst[5] & inst[2] & ~inst[0] & ~inst[1] | inst[28] & ~inst[27] & ~inst[26]);
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assign ctrl.ECtrl.OP.f_or = ~inst[31] & (~inst[28] & ~inst[29] & ~inst[27] & ~inst[26] & inst[5] & inst[2] & inst[0] | inst[28] & ~inst[27] & inst[26]);
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assign ctrl.ECtrl.OP.f_xor = ~inst[31] & (~inst[28] & ~inst[29] & ~inst[27] & ~inst[26] & inst[5] & inst[2] & ~inst[0] & inst[1] | inst[28] & inst[27]);
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assign ctrl.ECtrl.OP.f_slt = ~inst[31] & ~inst[28] & ~inst[26] & (~inst[29] & inst[5] & inst[3] & ~inst[2] & ~inst[0] | inst[27]);
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assign ctrl.ECtrl.OP.f_sltu = ~inst[31] & ~inst[28] & (~inst[26] & ~inst[29] & ~inst[27] & inst[5] & inst[3] & ~inst[2] & inst[0] | inst[26] & inst[29] & inst[27]);
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assign ctrl.ECtrl.OP.alt = ~inst[31] & (~inst[26] & (~inst[29] & inst[1] & (inst[5] | inst[0]) | inst[27]) | inst[26] & inst[29] & inst[27]);
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assign ctrl.ECtrl.OP.f_sl = ~inst[31] & ~inst[26] & ~inst[28] & ~inst[27] & ~inst[29] & ~inst[5] & ~inst[1] & ~inst[3];
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assign ctrl.ECtrl.OP.f_sr = ~inst[31] & ~inst[26] & ~inst[28] & ~inst[27] & ~inst[29] & ~inst[5] & inst[1];
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assign ctrl.ECtrl.OP.f_add = (~inst[26] & ~inst[28] & ~inst[27] & ((~inst[5] & ~inst[1] & inst[3] | inst[5] & ~inst[2] & ~inst[3]) | inst[29]) | inst[26] & (~inst[29] | (~inst[28] & ~inst[27] | inst[28] & inst[27]))) | inst[31];
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assign ctrl.ECtrl.OP.f_and = ~inst[31] & ~inst[26] & (~inst[28] & ~inst[27] & ~inst[29] & inst[5] & inst[2] & ~inst[0] & ~inst[1] | inst[28] & ~inst[27]);
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assign ctrl.ECtrl.OP.f_or = ~inst[31] & (~inst[26] & ~inst[28] & ~inst[27] & ~inst[29] & inst[5] & inst[2] & inst[0] | inst[26] & inst[29] & inst[28] & ~inst[27]);
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assign ctrl.ECtrl.OP.f_xor = ~inst[31] & ~inst[26] & (~inst[28] & ~inst[27] & ~inst[29] & inst[5] & inst[2] & ~inst[0] & inst[1] | inst[28] & inst[27]);
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assign ctrl.ECtrl.OP.f_slt = ~inst[31] & ~inst[26] & ~inst[28] & (~inst[29] & inst[5] & ~inst[2] & inst[3] & ~inst[0] | inst[27]);
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assign ctrl.ECtrl.OP.f_sltu = ~inst[31] & (~inst[26] & ~inst[28] & ~inst[27] & ~inst[29] & inst[5] & ~inst[2] & inst[3] & inst[0] | inst[26] & inst[29] & ~inst[28] & inst[27]);
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assign ctrl.ECtrl.OP.alt = ~inst[31] & (~inst[26] & (~inst[29] & inst[1] & (inst[0] | inst[5]) | inst[27]) | inst[26] & inst[27] & inst[29] & ~inst[28]);
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assign ctrl.ECtrl.SA = SA_t'({
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((~inst[26] & ~inst[28] & (~inst[27] & ((~inst[2] & inst[3] & inst[4] | inst[2] & ~inst[3]) | inst[5]) | inst[30]) | inst[31]) | inst[29]),
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~inst[30] & ((~inst[29] & (inst[3] | inst[2] | inst[4] | inst[5] | inst[27] | inst[28] | inst[26]) | inst[29] & (~inst[28] | ~inst[27] | ~inst[26])) | inst[31])
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});
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assign ctrl.ECtrl.SB = SB_t'({
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((inst[30] | inst[31]) | inst[29]),
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(~inst[5] & (~inst[1] & (~inst[0] & (~inst[3] & inst[4] | inst[3] & ~inst[4]) | inst[0] & (~inst[4] | ~inst[3])) | inst[1] & inst[4] & ~inst[3]) | inst[27] | inst[31] | inst[28] | inst[30] | inst[29] | inst[26])
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});
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assign ctrl.ECtrl.SA = SA_t'({inst[31] | (~inst[28] & (inst[29] | inst[26] | inst[5] | inst[3] | inst[2]) | inst[28] & (~inst[27] | ~inst[26])), inst[31] | inst[29] | ~inst[26] & (inst[5] | inst[2])});
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assign ctrl.ECtrl.SB = SB_t'({inst[31] | inst[29], inst[26] | ~inst[5] & inst[3]});
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assign ctrl.MCtrl0.HW = ~inst[26] & ~inst[29] & ~inst[30] & ~inst[28] & ~inst[27] & inst[4] & (~inst[1] & inst[0] | inst[3]);
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assign ctrl.MCtrl0.LW = ~inst[26] & ~inst[29] & ~inst[30] & ~inst[28] & ~inst[27] & inst[4] & (inst[1] & inst[0] | inst[3]);
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assign ctrl.MCtrl0.HW = ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[4] & (inst[3] | ~inst[1] & inst[0]);
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assign ctrl.MCtrl0.LW = ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[4] & (inst[3] | inst[1] & inst[0]);
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assign ctrl.MCtrl0.HLS = HLS_t'({~inst[3], inst[1:0]});
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assign ctrl.MCtrl0.C0D = inst[15:11];
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assign ctrl.MCtrl0.C0W = inst[30] & inst[23];
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assign ctrl.MCtrl0.RS0 = RS0_t'({
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~inst[4] | inst[26] | inst[29], ~inst[29] & ~inst[26] & inst[4] & ~inst[1] | inst[30]
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});
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assign ctrl.MCtrl0.RS0 = RS0_t'({inst[29] | inst[26] | ~inst[4], inst[30] | ~inst[29] & ~inst[26] & inst[4] & ~inst[1]});
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assign ctrl.MCtrl1.MR = inst[31];
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assign ctrl.MCtrl1.MR = inst[31];
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assign ctrl.MCtrl1.MWR = inst[29];
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assign ctrl.MCtrl1.MX = ~inst[28];
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assign ctrl.MCtrl1.SZ = inst[27:26];
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assign ctrl.MCtrl1.MX = ~inst[28];
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assign ctrl.MCtrl1.SZ = inst[27:26];
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assign ctrl.WCtrl.RW = (ctrl.RD != 5'b00000) & ~inst[30] & (~inst[29] & (~inst[31] & ~inst[28] & (~inst[27] & (~inst[26] & (~inst[3] & (~inst[4] | inst[4] & ~inst[0]) | inst[3] & (~inst[4] & ~inst[2] & inst[0] | inst[5])) | inst[26] & inst[20]) | inst[27] & inst[26]) | inst[31]) | inst[29] & ~inst[31]) | inst[30] & ~inst[25] & ~inst[23];
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assign ctrl.WCtrl.RW = ctrl.RD != 5'b00000 & (~inst[30] & (~inst[29] & (inst[31] | ~inst[28] & (~inst[27] & (~inst[26] & (~inst[3] & (~inst[4] | ~inst[0]) | inst[3] & (inst[5] | ~inst[4] & ~inst[2] & inst[0])) | inst[26] & inst[20]) | inst[27] & inst[26])) | inst[29] & ~inst[31]) | inst[30] & ~inst[25] & ~inst[23]);
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endmodule
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@ -183,8 +183,8 @@ module Datapath (
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logic M_I0_FT_W_I1;
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word_t M_I0_ForwardT;
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logic M_I1_RData_OK;
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word_t M_I1_RData;
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logic M_I1_DataR_OK;
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word_t M_I1_DataR;
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word_t HI;
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word_t LO;
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@ -202,7 +202,7 @@ module Datapath (
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PF_pcb,
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PF_pcjr,
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PF_pcj,
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D.IA.PFCtrl.PCS,
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D.IA.PCS,
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PF_pc0
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);
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prio_mux5 #(32) PF_pc_mux (
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@ -211,16 +211,16 @@ module Datapath (
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`PCEXC,
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C0_EPC,
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`PCRST,
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{~F_valid, M_exception.ERET, M_exception.ExcValid, ~D_IB_valid},
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{~F_valid, M_exception.ERET, M_exception.ExcValid, ~D_IB_valid | ~D.IA.BJRJ},
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PF.pc
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);
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assign rstD = D_IA_valid & D.IA.PFCtrl.PCS != PCP8 & D_IA_can_dispatch;
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assign rstD = D_IA_valid & D.IA.PCS != PCP8 & D_IA_can_dispatch;
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assign rstM = C0_exception.ExcValid;
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assign PF_go = ~D.IA_ExcValid & ~D.IB_ExcValid & ~E.I0.ExcValid & ~E.I1.ExcValid & PF.pc[1:0] == 2'b00;
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assign fetch_i.req = ~F_valid | M_exception.ExcValid
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| PF_go & (~D_IB_valid & ~IQ_valids[3] | (~D.IA.PFCtrl.BJRJ | D_readygo)
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| PF_go & (~D_IB_valid & ~IQ_valids[3] | (~D.IA.BJRJ | D_readygo)
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& (rstD
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| ~IQ_valids[3]
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| ~IQ_valids[2] & (PF.pc[2] | F.pc[2] | D_readygo)
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@ -377,53 +377,40 @@ module Datapath (
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assign D.IA_ExcValid = D_IA_valid & (D.IA_pc[1:0] != 2'b00 | ~D_IA_iv | D.IA.SYSCALL | D.IA.BREAK | D.IA.ERET);
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assign D.IA_ERET = D_IA_valid & D_IA_iv & D.IA.ERET;
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assign D.IA_ExcCode = D.IA_pc[1:0] != 2'b00 ? `EXCCODE_ADDRR : ~D_IA_iv ? `EXCCODE_RI : D.IA.SYSCALL ? `EXCCODE_SYSCALL : `EXCCODE_BREAK;
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assign D.IA_ExcCode = D.IA_pc[1:0] != 2'b00 ? `EXCCODE_ADDRR : ~D_IA_iv ? `EXCCODE_RI : D.IA_inst[0] ? `EXCCODE_SYSCALL : `EXCCODE_BREAK;
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assign D.IB_ExcValid = D_IB_valid & (D.IB_pc[1:0] != 2'b00 | ~D_IB_iv | D.IB.SYSCALL | D.IB.BREAK | D.IB.ERET | D.IB_Delay & D.IB.PFCtrl.BJRJ);
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assign D.IB_ExcValid = D_IB_valid & (D.IB_pc[1:0] != 2'b00 | ~D_IB_iv | D.IB.SYSCALL | D.IB.BREAK | D.IB.ERET | D.IB_Delay & D.IB.BJRJ);
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assign D.IB_ERET = D_IB_valid & D_IB_iv & D.IB.ERET & ~D.IB_Delay;
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assign D.IB_ExcCode = D.IB_pc[1:0] != 2'b00 ? `EXCCODE_ADDRR : ~D_IB_iv ? `EXCCODE_RI : D.IB.SYSCALL ? `EXCCODE_SYSCALL : D.IB.BREAK ? `EXCCODE_BREAK : `EXCCODE_RI;
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assign D.IB_Delay = D.IA.PFCtrl.BJRJ;
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assign D.IB_ExcCode = D.IB_pc[1:0] != 2'b00 ? `EXCCODE_ADDRR : (~D_IB_iv | D.IB.ERET | D.IB_Delay & D.IB.BJRJ) ? `EXCCODE_RI : D.IB_inst[0] ? `EXCCODE_SYSCALL : `EXCCODE_BREAK;
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assign D.IB_Delay = D.IA.BJRJ;
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// D.Dispatch
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assign D_IA_DataHazard = E.I0.WCtrl.RW & D.IA.RS == E.I0.RD & D.IA.ECtrl.SA == RS & E.I0.MCtrl.RS0 != ALUOut
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| E.I1.WCtrl.RW & D.IA.RS == E.I1.RD & D.IA.ECtrl.SA == RS & E.I1.MCtrl.MR
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| E.I0.WCtrl.RW & D.IA.RT == E.I0.RD & D.IA.ECtrl.SB == RT & E.I0.MCtrl.RS0 != ALUOut
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| E.I1.WCtrl.RW & D.IA.RT == E.I1.RD & D.IA.ECtrl.SB == RT & E.I1.MCtrl.MR
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| E.I0.WCtrl.RW & D.IA.RS == E.I0.RD & ~D.IA.DCtrl.DP1 & (D.IA.MCtrl0.HW | D.IA.MCtrl0.LW) & D.IA.MCtrl0.HLS != HLRS & E.I0.MCtrl.RS0 != ALUOut
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| E.I1.WCtrl.RW & D.IA.RS == E.I1.RD & ~D.IA.DCtrl.DP1 & (D.IA.MCtrl0.HW | D.IA.MCtrl0.LW) & D.IA.MCtrl0.HLS != HLRS & E.I1.MCtrl.MR
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| E.I0.WCtrl.RW & D.IA.RT == E.I0.RD & ~D.IA.DCtrl.DP1 & (D.IA.MCtrl0.HW | D.IA.MCtrl0.LW) & D.IA.MCtrl0.HLS != HLRS & E.I0.MCtrl.RS0 != ALUOut
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| E.I1.WCtrl.RW & D.IA.RT == E.I1.RD & ~D.IA.DCtrl.DP1 & (D.IA.MCtrl0.HW | D.IA.MCtrl0.LW) & D.IA.MCtrl0.HLS != HLRS & E.I1.MCtrl.MR
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| E.I0.WCtrl.RW & D.IA.RT == E.I0.RD & ~D.IA.DCtrl.DP0 & D.IA.MCtrl1.MR & D.IA.MCtrl1.MWR & E.I0.MCtrl.RS0 != ALUOut
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| E.I1.WCtrl.RW & D.IA.RT == E.I1.RD & ~D.IA.DCtrl.DP0 & D.IA.MCtrl1.MR & D.IA.MCtrl1.MWR & E.I1.MCtrl.MR
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| E.I1.WCtrl.RW & D.IA.RS == E.I1.RD & D.IA.PFCtrl.BJR
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| E.I0.WCtrl.RW & D.IA.RS == E.I0.RD & D.IA.PFCtrl.BJR
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| E.I0.WCtrl.RW & D.IA.RT == E.I0.RD & D.IA.PFCtrl.BE
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| E.I1.WCtrl.RW & D.IA.RT == E.I1.RD & D.IA.PFCtrl.BE
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| M.I0.WCtrl.RW & D.IA.RS == M.I0.RD & D.IA.PFCtrl.BJR & M.I0.MCtrl.RS0 != ALUOut
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| M.I1.WCtrl.RW & D.IA.RS == M.I1.RD & D.IA.PFCtrl.BJR & M.I1.MCtrl.MR
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| M.I0.WCtrl.RW & D.IA.RT == M.I0.RD & D.IA.PFCtrl.BE & M.I0.MCtrl.RS0 != ALUOut
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| M.I1.WCtrl.RW & D.IA.RT == M.I1.RD & D.IA.PFCtrl.BE & M.I1.MCtrl.MR;
|
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assign D_IA_DataHazard = E.I0.WCtrl.RW & D.IA.RS == E.I0.RD & D.IA.ES & E.I0.MCtrl.RS0 != ALUOut
|
||||
| E.I1.WCtrl.RW & D.IA.RS == E.I1.RD & D.IA.ES & E.I1.MCtrl.MR
|
||||
| E.I0.WCtrl.RW & D.IA.RT == E.I0.RD & D.IA.ET & E.I0.MCtrl.RS0 != ALUOut
|
||||
| E.I1.WCtrl.RW & D.IA.RT == E.I1.RD & D.IA.ET & E.I1.MCtrl.MR
|
||||
| E.I0.WCtrl.RW & D.IA.RS == E.I0.RD & D.IA.DS
|
||||
| E.I1.WCtrl.RW & D.IA.RS == E.I1.RD & D.IA.DS
|
||||
| E.I0.WCtrl.RW & D.IA.RT == E.I0.RD & D.IA.DT
|
||||
| E.I1.WCtrl.RW & D.IA.RT == E.I1.RD & D.IA.DT
|
||||
| M.I0.WCtrl.RW & D.IA.RS == M.I0.RD & D.IA.DS & M.I0.MCtrl.RS0 != ALUOut
|
||||
| M.I1.WCtrl.RW & D.IA.RS == M.I1.RD & D.IA.DS & M.I1.MCtrl.MR
|
||||
| M.I0.WCtrl.RW & D.IA.RT == M.I0.RD & D.IA.DT & M.I0.MCtrl.RS0 != ALUOut
|
||||
| M.I1.WCtrl.RW & D.IA.RT == M.I1.RD & D.IA.DT & M.I1.MCtrl.MR;
|
||||
|
||||
assign D_IB_DataHazard = E.I0.WCtrl.RW & D.IB.RS == E.I0.RD & D.IB.ECtrl.SA == RS & E.I0.MCtrl.RS0 != ALUOut
|
||||
| E.I1.WCtrl.RW & D.IB.RS == E.I1.RD & D.IB.ECtrl.SA == RS & E.I1.MCtrl.MR
|
||||
| E.I0.WCtrl.RW & D.IB.RT == E.I0.RD & D.IB.ECtrl.SB == RT & E.I0.MCtrl.RS0 != ALUOut
|
||||
| E.I1.WCtrl.RW & D.IB.RT == E.I1.RD & D.IB.ECtrl.SB == RT & E.I1.MCtrl.MR
|
||||
| E.I0.WCtrl.RW & D.IB.RS == E.I0.RD & ~D.IB.DCtrl.DP1 & (D.IB.MCtrl0.HW | D.IB.MCtrl0.LW) & D.IB.MCtrl0.HLS != HLRS & E.I0.MCtrl.RS0 != ALUOut
|
||||
| E.I1.WCtrl.RW & D.IB.RS == E.I1.RD & ~D.IB.DCtrl.DP1 & (D.IB.MCtrl0.HW | D.IB.MCtrl0.LW) & D.IB.MCtrl0.HLS != HLRS & E.I1.MCtrl.MR
|
||||
| E.I0.WCtrl.RW & D.IB.RT == E.I0.RD & ~D.IB.DCtrl.DP1 & (D.IB.MCtrl0.HW | D.IB.MCtrl0.LW) & D.IB.MCtrl0.HLS != HLRS & E.I0.MCtrl.RS0 != ALUOut
|
||||
| E.I1.WCtrl.RW & D.IB.RT == E.I1.RD & ~D.IB.DCtrl.DP1 & (D.IB.MCtrl0.HW | D.IB.MCtrl0.LW) & D.IB.MCtrl0.HLS != HLRS & E.I1.MCtrl.MR
|
||||
| E.I0.WCtrl.RW & D.IB.RT == E.I0.RD & ~D.IB.DCtrl.DP0 & D.IB.MCtrl1.MR & D.IB.MCtrl1.MWR & E.I0.MCtrl.RS0 != ALUOut
|
||||
| E.I1.WCtrl.RW & D.IB.RT == E.I1.RD & ~D.IB.DCtrl.DP0 & D.IB.MCtrl1.MR & D.IB.MCtrl1.MWR & E.I1.MCtrl.MR
|
||||
| D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & D.IB.ECtrl.SA == RS
|
||||
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.ECtrl.SB == RT
|
||||
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & ~D.IB.DCtrl.DP0 & D.IB.MCtrl1.MR & D.IB.MCtrl1.MWR
|
||||
| D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & ~D.IB.DCtrl.DP1 & (D.IB.MCtrl0.HW | D.IB.MCtrl0.LW) & D.IB.MCtrl0.HLS == HLRS & ~D.IA.DCtrl.DP0 & D.IA.MCtrl1.MR
|
||||
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & ~D.IB.DCtrl.DP1 & D.IB.MCtrl0.C0W & ~D.IA.DCtrl.DP0 & D.IA.MCtrl1.MR;
|
||||
assign D_IB_DataHazard = E.I0.WCtrl.RW & D.IB.RS == E.I0.RD & D.IB.ES & E.I0.MCtrl.RS0 != ALUOut
|
||||
| E.I1.WCtrl.RW & D.IB.RS == E.I1.RD & D.IB.ES & E.I1.MCtrl.MR
|
||||
| E.I0.WCtrl.RW & D.IB.RT == E.I0.RD & D.IB.ET & E.I0.MCtrl.RS0 != ALUOut
|
||||
| E.I1.WCtrl.RW & D.IB.RT == E.I1.RD & D.IB.ET & E.I1.MCtrl.MR
|
||||
| D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & D.IB.ES
|
||||
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.ET
|
||||
| D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & ~D.IB.DP1 & (D.IB.MCtrl0.HW ^ D.IB.MCtrl0.LW) & ~D.IA.DP0
|
||||
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & ~D.IB.DP1 & D.IB.MCtrl0.C0W & ~D.IA.DP0;
|
||||
|
||||
assign D.A = (D.IA.DCtrl.DP0 & D.IA.DCtrl.DP1 | D.IA_ExcValid) ? D.IB.DCtrl.DP0 : D.IA.DCtrl.DP1;
|
||||
assign D.A = (D.IA.DP0 & D.IA.DP1 | D.IA_ExcValid) ? D.IB.DP0 : D.IA.DP1;
|
||||
|
||||
assign D_IA_can_dispatch = ~D_IA_valid | D.IA_ExcValid | ~D_IA_DataHazard & (~D.IA.PFCtrl.BJRJ | D_IB_valid);
|
||||
assign D_IB_can_dispatch = ~D_IB_valid | D.IB_ExcValid | ~D_IB_DataHazard & ~D.IB.PFCtrl.BJRJ & (D.A ? D.IB.DCtrl.DP0 : D.IB.DCtrl.DP1);
|
||||
assign D_IA_can_dispatch = ~D_IA_valid | D.IA_ExcValid | ~D_IA_DataHazard & (~D.IA.BJRJ | D_IB_valid);
|
||||
assign D_IB_can_dispatch = ~D_IB_valid | D.IB_ExcValid | ~D_IB_DataHazard & ~D.IB.BJRJ & (D.A ? D.IB.DP0 : D.IB.DP1);
|
||||
|
||||
assign D_readygo = ~D_IA_valid | ~D_IB_valid | D_IA_can_dispatch & E.en;
|
||||
assign D_readygo1 = ~D_IA_valid | D_IB_can_dispatch & D_IA_can_dispatch & E.en;
|
||||
@ -431,7 +418,7 @@ module Datapath (
|
||||
assign D.en0 = ~D_IA_valid | ~D_IB_valid | D_go & E.en;
|
||||
assign D.en1 = ~D_IA_valid | D_IB_can_dispatch & D_go & E.en;
|
||||
|
||||
assign D_go = (~PF_go | D.IA.PFCtrl.PCS == PCP8 | fetch_i.req & fetch_i.addr_ok) & D_IA_can_dispatch | D.IA_ExcValid;
|
||||
assign D_go = (~PF_go | D.IA.PCS == PCP8 | fetch_i.req & fetch_i.addr_ok) & D_IA_can_dispatch | D.IA_ExcValid;
|
||||
assign D_IA_go = D_IA_valid & ~D.IA_ExcValid;
|
||||
assign D_IB_go = D_IB_valid & ~D.IB_ExcValid & D_IB_can_dispatch & ~D.IA_ExcValid;
|
||||
|
||||
@ -570,12 +557,10 @@ module Datapath (
|
||||
E.en,
|
||||
{E.I0.imm, E.I0.sa}
|
||||
);
|
||||
ffenrc #(13) E_I0_ECtrl_ff (
|
||||
ffen #(13) E_I0_ECtrl_ff (
|
||||
clk,
|
||||
rst | rstM,
|
||||
D.I0.ECtrl,
|
||||
E.en,
|
||||
~D_go | ~D_I0_go,
|
||||
E.I0.ECtrl
|
||||
);
|
||||
ffenrc #(13) E_I0_MCtrl_ff (
|
||||
@ -627,12 +612,10 @@ module Datapath (
|
||||
E.en,
|
||||
{E.I1.imm, E.I1.sa}
|
||||
);
|
||||
ffenrc #(13) E_I1_ECtrl_ff (
|
||||
ffen #(13) E_I1_ECtrl_ff (
|
||||
clk,
|
||||
rst | rstM,
|
||||
D.I1.ECtrl,
|
||||
E.en,
|
||||
~D_go | ~D_I1_go,
|
||||
E.I1.ECtrl
|
||||
);
|
||||
ffenrc #(5) E_I1_MCtrl_ff (
|
||||
@ -907,10 +890,13 @@ module Datapath (
|
||||
|
||||
// M.Exc
|
||||
assign M.I0.BadVAddr = M.I0.pc;
|
||||
assign M_exception = ~M.I0.ExcValid | M.I1.ExcValid & M.A ? {
|
||||
M.I1.ExcValid, M.I1.Delay, M.I1.ExcCode, M.I1.BadVAddr, M.I1.pc, M.I1.ERET
|
||||
} : {
|
||||
M.I0.ExcValid, M.I0.Delay, M.I0.ExcCode, M.I0.BadVAddr, M.I0.pc, M.I0.ERET
|
||||
assign M_exception = {
|
||||
M.I1.ExcValid | M.I0.ExcValid,
|
||||
~M.I0.ExcValid | M.I1.ExcValid & M.A ? {
|
||||
M.I1.Delay, M.I1.ExcCode, M.I1.BadVAddr, M.I1.pc, M.I1.ERET
|
||||
} : {
|
||||
M.I0.Delay, M.I0.ExcCode, M.I0.BadVAddr, M.I0.pc, M.I0.ERET
|
||||
}
|
||||
};
|
||||
assign C0_exception = {
|
||||
M_exception.ExcValid & M.en,
|
||||
@ -967,16 +953,16 @@ module Datapath (
|
||||
|
||||
// M.I1.MEM
|
||||
mux4 #(8) M_I1_Byte_mux (
|
||||
M_I1_RData[7:0],
|
||||
M_I1_RData[15:8],
|
||||
M_I1_RData[23:16],
|
||||
M_I1_RData[31:24],
|
||||
M_I1_DataR[7:0],
|
||||
M_I1_DataR[15:8],
|
||||
M_I1_DataR[23:16],
|
||||
M_I1_DataR[31:24],
|
||||
M.I1.ALUOut[1:0],
|
||||
M_I1_Byte
|
||||
);
|
||||
mux2 #(16) M_I1_Half_mux (
|
||||
M_I1_RData[15:0],
|
||||
M_I1_RData[31:16],
|
||||
M_I1_DataR[15:0],
|
||||
M_I1_DataR[31:16],
|
||||
M.I1.ALUOut[1],
|
||||
M_I1_Half
|
||||
);
|
||||
@ -993,28 +979,28 @@ module Datapath (
|
||||
mux3 #(32) M_I1_MData_mux (
|
||||
M_I1_ByteX,
|
||||
M_I1_HalfX,
|
||||
M_I1_RData,
|
||||
M_I1_DataR,
|
||||
M.I1.MCtrl.SZ,
|
||||
M_I1_MData
|
||||
);
|
||||
mux2 #(32) M_I1_RDataW_mux (
|
||||
mux2 #(32) M_I1_DataRW_mux (
|
||||
M.I1.ALUOut,
|
||||
M_I1_MData,
|
||||
M.I1.MCtrl.MR,
|
||||
M.I1.RDataW
|
||||
);
|
||||
|
||||
buffer #(32) M_I1_RData_buffer (
|
||||
buffer #(32) M_I1_DataR_buffer (
|
||||
clk, rst,
|
||||
mem_i.data_ok,
|
||||
mem_i.rdata,
|
||||
M.en,
|
||||
M_I1_RData_OK,
|
||||
M_I1_RData
|
||||
M_I1_DataR_OK,
|
||||
M_I1_DataR
|
||||
);
|
||||
|
||||
assign M.en = M_go & W.en;
|
||||
assign M_go = (~M.I1.MCtrl.MR | M_I1_RData_OK) & (~M_exception.ExcValid | fetch_i.req & fetch_i.addr_ok);
|
||||
assign M_go = (~M.I1.MCtrl.MR | M_I1_DataR_OK) & (~M_exception.ExcValid | fetch_i.req & fetch_i.addr_ok);
|
||||
|
||||
// M.Forwarding
|
||||
assign M_I0_FS_M_I1 = M.A & M.I1.WCtrl.RW & M.I0.RS == M.I1.RD;
|
||||
@ -1050,6 +1036,14 @@ module Datapath (
|
||||
W.en,
|
||||
W.A
|
||||
);
|
||||
`ifdef SIMULATION_PC
|
||||
ffen #(64) W_I01_pc_ff (
|
||||
clk,
|
||||
{M.I0.pc, M.I1.pc},
|
||||
W.en,
|
||||
{W.I0.pc, W.I1.pc}
|
||||
);
|
||||
`endif
|
||||
ffen #(32) W_I0_RDataW_ff (
|
||||
clk,
|
||||
M.I0.RDataW,
|
||||
@ -1078,14 +1072,6 @@ module Datapath (
|
||||
~M_go,
|
||||
{W.I1.RD, W.I1.WCtrl}
|
||||
);
|
||||
`ifdef SIMULATION_PC
|
||||
ffen #(64) W_I01_pc_ff (
|
||||
clk,
|
||||
{M.I0.pc, M.I1.pc},
|
||||
W.en,
|
||||
{W.I0.pc, W.I1.pc}
|
||||
);
|
||||
`endif
|
||||
|
||||
assign W.en = 1'b1;
|
||||
|
||||
|
||||
@ -55,7 +55,7 @@ typedef enum logic [1:0] {
|
||||
typedef enum logic [1:0] {
|
||||
RT = 2'b00,
|
||||
EIGHT = 2'b01,
|
||||
IMM = 2'b11
|
||||
IMM = 2'b11 // 2'b1?
|
||||
} SB_t;
|
||||
|
||||
typedef enum logic [1:0] {
|
||||
@ -74,20 +74,8 @@ typedef enum logic [2:0] {
|
||||
} HLS_t;
|
||||
|
||||
typedef struct packed {
|
||||
PCS_t PCS;
|
||||
logic BJRJ;
|
||||
logic BJR;
|
||||
logic BE;
|
||||
} PFCtrl_t;
|
||||
|
||||
typedef struct packed {
|
||||
logic DP0;
|
||||
logic DP1;
|
||||
} DCtrl_t;
|
||||
|
||||
typedef struct packed {
|
||||
SA_t SA; // critical
|
||||
SB_t SB; // critical
|
||||
SA_t SA;
|
||||
SB_t SB;
|
||||
aluctrl_t OP;
|
||||
} ECtrl_t;
|
||||
|
||||
@ -97,7 +85,7 @@ typedef struct packed {
|
||||
logic LW; // critical
|
||||
logic [4:0] C0D;
|
||||
logic C0W; // critical
|
||||
HLS_t HLS; // critical
|
||||
HLS_t HLS;
|
||||
} MCtrl0_t;
|
||||
|
||||
typedef struct packed {
|
||||
@ -120,9 +108,14 @@ typedef struct packed {
|
||||
logic [4:0] RS;
|
||||
logic [4:0] RT;
|
||||
|
||||
PFCtrl_t PFCtrl;
|
||||
|
||||
DCtrl_t DCtrl;
|
||||
PCS_t PCS;
|
||||
logic BJRJ;
|
||||
logic DP0;
|
||||
logic DP1;
|
||||
logic DS;
|
||||
logic DT;
|
||||
logic ES;
|
||||
logic ET;
|
||||
|
||||
ECtrl_t ECtrl;
|
||||
|
||||
|
||||
@ -13,32 +13,36 @@ def gini(d):
|
||||
g -= (sum(1 for k, v in d if v == i) / len(d)) ** 2
|
||||
return g
|
||||
|
||||
def merge(s, t):
|
||||
def readable_and(s, t):
|
||||
if(len(t) == 0):
|
||||
return s
|
||||
return s + ' & ' + t
|
||||
|
||||
def union(d0, d1, i):
|
||||
def readable_merge(d0, d1, i):
|
||||
d = d0 | d1
|
||||
for k in d:
|
||||
if(k not in d0):
|
||||
d[k] = merge('[{}]'.format(i), d1[k])
|
||||
d[k] = readable_and('[{}]'.format(i), d1[k])
|
||||
elif(k not in d1):
|
||||
d[k] = merge('~[{}]'.format(i), d0[k])
|
||||
d[k] = readable_and('~[{}]'.format(i), d0[k])
|
||||
else:
|
||||
d[k] = '({} | {})'.format(merge('~[{}]'.format(i), d0[k]), merge('[{}]'.format(i), d1[k]))
|
||||
d[k] = '({} | {})'.format(readable_and('~[{}]'.format(i), d0[k]), readable_and('[{}]'.format(i), d1[k]))
|
||||
return d
|
||||
|
||||
def solve(d):
|
||||
def solve(d, mask = 0):
|
||||
if(len(d) == 0):
|
||||
return {}
|
||||
s = set(v for k, v in d)
|
||||
if(len(s) == 1):
|
||||
return {s.pop(): ''}
|
||||
min_gini = -1
|
||||
min_idx = -1
|
||||
for i in range(0, bits):
|
||||
if(mask & 1 << i):
|
||||
continue
|
||||
s0 = [(k, v) for k, v in d if k[i] == '0']
|
||||
s1 = [(k, v) for k, v in d if k[i] == '1']
|
||||
if(len(s0) + len(s1) != len(d)):
|
||||
if(len(s0) + len(s1) != len(d) or len(s0) == 0 or len(s1) == 0):
|
||||
continue
|
||||
g = gini(s0) * len(s0) / len(d) + gini(s1) * len(s1) / len(d)
|
||||
if(min_idx == -1 or g < min_gini):
|
||||
@ -48,9 +52,12 @@ def solve(d):
|
||||
raise "fuck"
|
||||
s0 = [(k, v) for k, v in d if k[min_idx] == '0']
|
||||
s1 = [(k, v) for k, v in d if k[min_idx] == '1']
|
||||
return union(solve(s0), solve(s1), bits - 1 - min_idx)
|
||||
return readable_merge(solve(s0, mask | 1 << min_idx), solve(s1, mask | 1 << min_idx), bits - 1 - min_idx)
|
||||
|
||||
for i in range(1, len(title)):
|
||||
print(title[i])
|
||||
ans = solve([(item[0][preq:], item[i]) for item in items if item[i] != '?'])
|
||||
kind = set(item[i] for item in items if item[i] != '?')
|
||||
if(len(kind) == 4):
|
||||
print(4)
|
||||
print(ans)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user