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fix3

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This commit is contained in:
cxy004 2021-07-30 03:31:42 +08:00
parent 5f8e8a8c6a
commit 99436d9a42
5 changed files with 34 additions and 29 deletions
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18
src/Core/Controller.sv
View File

@ -35,9 +35,8 @@ module Controller (
assign ctrl.RT = inst[20:16];
assign ctrl.PFCtrl.PCS = PCS_t'({
~inst[28] & (~inst[27] & ~inst[26] & ~inst[31] & ~inst[30] & ~inst[29] & inst[3] & ~inst[4] & ~inst[5] | inst[27] & ~inst[29] & ~inst[31]),
~inst[26] & (~inst[27] & inst[28] & ~inst[31] & ~inst[29] & eq | inst[27] & ~inst[29] & (~inst[28] | eq & ltz)) | inst[26] & ~inst[29] & ~inst[31] & (~inst[27] & ~inst[30] & (~inst[28] & (~ltz & inst[16] | ltz & ~inst[16]) | inst[28] & ~eq) | inst[27] & (~inst[28] | ~eq | ~ltz))
});
~inst[27] & ~inst[26] & ~inst[28] & ~inst[31] & ~inst[30] & ~inst[29] & inst[3] & ~inst[4] & ~inst[5] | inst[27] & ~inst[28] & ~inst[29] & ~inst[31],
~inst[26] & (~inst[27] & inst[28] & ~inst[31] & ~inst[29] & eq | inst[27] & ~inst[29] & (~inst[28] | ltz | eq)) | inst[26] & ~inst[29] & ~inst[31] & (~inst[28] & (~ltz & inst[16] | ltz & ~inst[16] | inst[27]) | inst[28] & ~eq & (~inst[27] | ~ltz))});
assign ctrl.PFCtrl.BJRJ = ~inst[26] & (~inst[27] & (~inst[28] & ~inst[30] & ~inst[31] & ~inst[29] & inst[3] & ~inst[4] & ~inst[5] & ~inst[2] | inst[28] & ~inst[31] & ~inst[29]) | inst[27] & ~inst[29]) | inst[26] & ~inst[29] & ~inst[31];
assign ctrl.PFCtrl.BJR = ~inst[26] & (~inst[28] & ~inst[30] & ~inst[29] & ~inst[31] & ~inst[27] & inst[3] & ~inst[4] & ~inst[5] & ~inst[2] | inst[28] & ~inst[29] & ~inst[31]) | inst[26] & ~inst[29] & ~inst[31] & (~inst[27] | inst[27] & inst[28]);
assign ctrl.PFCtrl.BE = inst[28] & ~inst[29] & ~inst[31] & ~inst[27];
@ -45,14 +44,15 @@ module Controller (
assign ctrl.DCtrl.DP0 = ~inst[31];
assign ctrl.DCtrl.DP1 = ~inst[30] & (~inst[26] & (~inst[29] & (~inst[28] & (~inst[31] & (~inst[27] & ~inst[4] | inst[27]) | inst[31]) | inst[28]) | inst[29]) | inst[26]) | inst[30] & inst[25];
assign ctrl.ECtrl.OP.f_sr = ~inst[31] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & ~inst[5] & ~inst[3] & (~inst[2] | inst[1]);
assign ctrl.ECtrl.OP.f_sl = ~inst[31] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & ~inst[5] & ~inst[3] & inst[2] & ~inst[1];
assign ctrl.ECtrl.OP.f_add = ((~inst[26] & ~inst[28] & ~inst[27] & ((~inst[5] & inst[3] | inst[5] & ~inst[3] & ~inst[2]) | inst[29]) | inst[26] & (~inst[29] | (~inst[28] & ~inst[27] | inst[28] & inst[27]))) | inst[31]);
assign ctrl.ECtrl.OP.f_slt = ~inst[31] & ~inst[26] & ~inst[28] & (~inst[29] & inst[5] & inst[3] & ~inst[2] & ~inst[0] | inst[27]);
assign ctrl.ECtrl.OP.f_sltu = ~inst[31] & (~inst[26] & ~inst[28] & ~inst[27] & ~inst[29] & inst[5] & ~inst[2] & inst[3] & inst[0] | inst[26] & inst[29] & ~inst[28] & inst[27]);
assign ctrl.ECtrl.OP.f_sl = ~inst[31] & ~inst[26] & ~inst[28] & ~inst[27] & ~inst[29] & ~inst[5] & ~inst[1] & ~inst[3];
assign ctrl.ECtrl.OP.f_sr = ~inst[31] & ~inst[26] & ~inst[28] & ~inst[27] & ~inst[29] & ~inst[5] & inst[1];
assign ctrl.ECtrl.OP.f_add = (~inst[26] & ~inst[28] & ~inst[27] & ((~inst[5] & ~inst[1] & inst[3] | inst[5] & ~inst[2] & ~inst[3]) | inst[29]) | inst[26] & (~inst[29] | (~inst[28] & ~inst[27] | inst[28] & inst[27]))) | inst[31];
assign ctrl.ECtrl.OP.f_and = ~inst[31] & ~inst[26] & (~inst[28] & ~inst[27] & ~inst[29] & inst[5] & inst[2] & ~inst[0] & ~inst[1] | inst[28] & ~inst[27]);
assign ctrl.ECtrl.OP.f_xor = ~inst[31] & ~inst[26] & (~inst[28] & ~inst[27] & ~inst[29] & inst[5] & inst[2] & ~inst[0] & inst[1] | inst[28] & inst[27]);
assign ctrl.ECtrl.OP.f_or = ~inst[31] & (~inst[26] & ~inst[28] & ~inst[27] & ~inst[29] & inst[5] & inst[2] & inst[0] | inst[26] & inst[29] & inst[28] & ~inst[27]);
assign ctrl.ECtrl.OP.f_xor = ~inst[31] & ~inst[26] & (~inst[28] & ~inst[27] & ~inst[29] & inst[5] & inst[2] & ~inst[0] & inst[1] | inst[28] & inst[27]);
assign ctrl.ECtrl.OP.f_slt = ~inst[31] & ~inst[26] & ~inst[28] & (~inst[29] & inst[5] & ~inst[2] & inst[3] & ~inst[0] | inst[27]);
assign ctrl.ECtrl.OP.f_sltu = ~inst[31] & (~inst[26] & ~inst[28] & ~inst[27] & ~inst[29] & inst[5] & ~inst[2] & inst[3] & inst[0] | inst[26] & inst[29] & ~inst[28] & inst[27]);
assign ctrl.ECtrl.OP.alt = ~inst[31] & (~inst[26] & (~inst[29] & inst[1] & (inst[0] | inst[5]) | inst[27]) | inst[26] & inst[27] & inst[29] & ~inst[28]);
assign ctrl.ECtrl.SA = SA_t'({
((~inst[26] & ~inst[28] & (~inst[27] & ((~inst[2] & inst[3] & inst[4] | inst[2] & ~inst[3]) | inst[5]) | inst[30]) | inst[31]) | inst[29]),

19
src/Core/Datapath.sv
View File

@ -207,19 +207,19 @@ module Datapath (
PF.pc
);
assign rstD = D.IA.PFCtrl.PCS != PCP8;
assign rstD = D.IA.PFCtrl.PCS != PCP8 & D_IA_can_dispatch;
assign rstM = C0_exception.ExcValid;
assign PF_req = ~D.IA_ExcValid & ~D.IB_ExcValid & ~E.I0.ExcValid & ~E.I1.ExcValid;
assign PF_go = PF.pc[1:0] == 2'b00 & PF_req;
assign fetch_i.req = rst | C0_exception.ExcValid | C0_exception.ERET | ~D_IA_valid | D_readygo
assign fetch_i.req = rst | C0_exception.ExcValid | C0_exception.ERET | ~D_IA_valid
| PF_go & (~D.IA.PFCtrl.BJRJ | D_IA_can_dispatch)
& ( ~IQ_valids[3]
| ~IQ_valids[2] & (PF.pc[2] | F.pc[2] | D_readygo | D_readygo1)
| ~IQ_valids[1] & (PF.pc[2] & (F.pc[2] | D_readygo | D_readygo1) | F.pc[2] & (D_readygo | D_readygo1) | D_readygo & D_readygo1)
| ~IQ_valids[0] & (PF.pc[2] & (F.pc[2] & (D_readygo | D_readygo1) | D_readygo & D_readygo1) | F.pc[2] & D_readygo & D_readygo1)
| IQ_valids[0] & PF.pc[2] & F.pc[2] & D_readygo & D_readygo1);
assign fetch_i.addr = PF.pc;
assign fetch_i.addr = {PF.pc[31:3], 3'b000};
//---------------------------------------------------------------------------//
// Fetch Stage //
@ -688,9 +688,11 @@ module Datapath (
);
// E.I1.MEM
strb E_I1_strb (
E.I1.MCtrl.SZ,
woutput E_I1_woutput (
mem_i.addr[1:0],
E_I1_ForwardT,
E.I1.MCtrl.SZ,
mem_i.wdata,
mem_i.wstrb,
E_I1_STRBERROR
);
@ -698,7 +700,6 @@ module Datapath (
assign mem_i.req = E.I1.MCtrl.MR & E_I1_go & M.en & ~rstM;
assign mem_i.wr = E.I1.MCtrl.MWR;
assign mem_i.addr = E.I1.ALUOut;
assign mem_i.wdata = E_I1_ForwardT;
assign E.en = E_go & M.en;
assign E_go = ~mem_i.req | mem_i.addr_ok;
@ -1006,7 +1007,7 @@ module Datapath (
clk,
rst,
{M.I0.RD, M.I0.WCtrl},
M.en,
W.en,
~M_go,
{W.I0.RD, W.I0.WCtrl}
);
@ -1020,7 +1021,7 @@ module Datapath (
clk,
rst,
{M.I1.RD, M.I1.WCtrl},
M.en,
W.en,
~M_go,
{W.I1.RD, W.I1.WCtrl}
);
@ -1029,7 +1030,7 @@ module Datapath (
clk,
rst,
{M.I0.pc, M.I1.pc},
M.en,
W.en,
~M_go,
{W.I0.pc, W.I1.pc}
);

22
src/Core/Gadgets.sv
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@ -81,29 +81,33 @@ module instr_valid (
endcase
endmodule
module strb (
input logic [1:0] size,
module woutput (
input logic [1:0] addr,
output logic [3:0] strb,
input word_t data,
input logic [1:0] size,
output word_t wdata,
output logic [3:0] wstrb,
output logic error
);
always_comb
casez (size)
2'b1?: begin
strb = 4'b1111;
wdata = data;
wstrb = 4'b1111;
error = (addr != 2'b00);
end
2'b01: begin
strb = addr[1] ? 4'b1100 : 4'b0011;
wdata = addr[1] ? data[31:16] : data[15:0];
wstrb = addr[1] ? 4'b1100 : 4'b0011;
error = (addr[0] != 1'b0);
end
2'b00: begin
case (addr)
2'b11: strb = 4'b1000;
2'b10: strb = 4'b0100;
2'b01: strb = 4'b0010;
2'b00: strb = 4'b0001;
2'b11: begin wdata = data[31:24]; wstrb = 4'b1000; end
2'b10: begin wdata = data[23:16]; wstrb = 4'b0100; end
2'b01: begin wdata = data[15: 8]; wstrb = 4'b0010; end
2'b00: begin wdata = data[ 7: 0]; wstrb = 4'b0001; end
endcase
error = 1'b0;
end

2
src/MyCPU.sv
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@ -86,7 +86,7 @@ module mycpu_top (
word_t C0_wdata;
EXCEPTION_t C0_exception;
word_t C0_EPC;
logic [2:0] K0;
logic [3:0] K0;
AXI axi (

2
tools/ctrl.txt
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@ -1,5 +1,5 @@
////-------------------------------- ERET SYSCALL BREAK PCS BJRJ BJR BE DP0 DP1 UI IX SA SB OP ALT OFA MR MWR MX RD RW RS0 HW LW C0W HLS
32'b00000000000???????????????000000 0 0 0 ? 0 0 0 1 1 ? ? SA RT SR 0 0 0 ? ? RD 1 ALUOut 0 0 0 ?
32'b00000000000???????????????000000 0 0 0 ? 0 0 0 1 1 ? ? SA RT SL 0 0 0 ? ? RD 1 ALUOut 0 0 0 ?
32'b00000000000???????????????000010 0 0 0 ? 0 0 0 1 1 ? ? SA RT SR 0 0 0 ? ? RD 1 ALUOut 0 0 0 ?
32'b00000000000???????????????000011 0 0 0 ? 0 0 0 1 1 ? ? SA RT SR 1 0 0 ? ? RD 1 ALUOut 0 0 0 ?
32'b000000???????????????00000000100 0 0 0 ? 0 0 0 1 1 ? ? RS RT SL ? 0 0 ? ? RD 1 ALUOut 0 0 0 ?