|
f256abd248
|
add control signals
|
2021-09-02 19:05:23 +08:00 |
|
|
53c0c018bb
|
fix bug in decode
|
2021-08-31 21:11:59 +08:00 |
|
|
0b872c9b7c
|
add sync pref as nop
|
2021-08-30 13:11:40 +08:00 |
|
|
54c6794a77
|
add LWL and LWR
|
2021-08-26 18:32:55 +08:00 |
|
|
8d039f4327
|
handle CpU exception
|
2021-08-25 20:59:32 +08:00 |
|
|
ba546d1d5f
|
add tlbwr datapath
|
2021-08-24 16:23:57 +08:00 |
|
cxy004
|
67ccb57eda
|
RW & RS0 fix
tools update
|
2021-08-18 12:16:28 +08:00 |
|
|
bc549d8bd4
|
1. tlb control signals
2. exccode rename
3. tlb datapath partial
Co-authored-by: cxy004 <cxy004@qq.com>
Co-authored-by: Hooo1941 <Hooo1941@users.noreply.github.com>
|
2021-08-11 12:58:02 +08:00 |
|
cxy004
|
8002b8c56a
|
simplify
|
2021-08-01 15:46:53 +08:00 |
|
|
d2b4570c9e
|
controller + prefetch + iq
Co-authored-by: Hooo1941 <Hooo1941@users.noreply.github.com>
Co-authored-by: cxy004 <cxy004@qq.com>
|
2021-07-26 22:29:59 +08:00 |
|
Hooo1941
|
d0839f6423
|
instrqueue
|
2021-07-07 16:55:10 +08:00 |
|
cxy004
|
9113c47b74
|
ctrl maker
|
2021-07-07 13:32:23 +08:00 |
|
cxy004
|
304ae7f8ce
|
ctrl tools & gadgets & interfaces
|
2021-07-05 15:25:15 +08:00 |
|