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62b26e3ab2
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fix trap
add testcases
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2021-09-22 16:26:40 +08:00 |
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a0d3367f34
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update ALU and test
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2021-09-07 19:53:53 +08:00 |
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7e85ca17e3
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refactor D-Cache CACHE inst
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2021-09-06 22:36:37 +08:00 |
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0cd3d9007e
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1. fix D-Cache clear by index
2. fix testcases
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2021-09-06 09:27:22 +08:00 |
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9df689ed7a
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refactor CACHE inst on D-CACHE
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2021-09-05 23:59:23 +08:00 |
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f8d7b7b0c6
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1. fix exceptions about CACHE inst on D-Cache
2. fix D-Cache control signals
3. fix I-Cache tag1 signal
4. fix I-Cache clear index logic
5. enhance D-Cache tests
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2021-09-05 13:06:35 +08:00 |
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1f2d7f6f3c
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1. fix deadlock on continuous CACHE inst
2. enhance the testcases
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2021-09-04 21:07:00 +08:00 |
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e08ded2242
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Test Passed? maybe
1. fix timing loop
2. fix multi driven
3. fix CACHE I-Cache Index logic
4. fix testcase
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2021-09-04 16:31:25 +08:00 |
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fa0c8ece07
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1. fix index addr
2. add n99 I-Cache CACHE test
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2021-09-03 22:16:59 +08:00 |
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17f64e1f2f
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1. add cache (D-Cache Address) inst
2. fix bug in ALR
3. fix bug in MMU and DCache
4. Register File rst
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2021-09-02 19:20:19 +08:00 |
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b0a9cd857c
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fix bug in MADD MADDU MSUB MSUBU
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2021-08-31 20:43:49 +08:00 |
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0269228c3c
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add test
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2021-08-31 19:32:39 +08:00 |
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2f22688aca
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update README.md and fix bug in inst test
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2021-08-30 15:59:21 +08:00 |
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94ab693971
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update gadgets
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2021-08-30 14:23:04 +08:00 |
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eea7b6bbda
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add lwl lwr swl swr test cases
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2021-08-29 20:17:42 +08:00 |
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62b8efb8e3
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lwl/lwr: fix bug in addr and strberror
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2021-08-27 22:25:42 +08:00 |
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6fe89863b0
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1. tlb test PASS
2. testbench.sv
Co-authored-by: cxy004 <cxy004@qq.com>
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2021-08-13 18:28:04 +08:00 |
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22e469ceec
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1. tlb: add soft
2. datapath OFA fix2
3. datapath C0 hazard
4. MMU buffer
Co-authored-by: cxy004 <cxy004@qq.com>
Co-authored-by: Hooo1941 <Hooo1941@users.noreply.github.com>
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2021-08-12 21:38:30 +08:00 |
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6b32775ada
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add system test
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2021-08-03 15:30:27 +08:00 |
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86b6dc7a3d
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fix perf tb
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2021-08-03 15:28:11 +08:00 |
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35f61a6dfd
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fix mmu
|
2021-08-01 15:48:30 +08:00 |
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269816582d
|
perf testbench
Co-authored-by: cxy004 <cxy004@qq.com>
Co-authored-by: Hooo1941 <Hooo1941@users.noreply.github.com>
|
2021-08-01 10:42:20 +08:00 |
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9601995c06
|
fix tb2
|
2021-07-31 10:48:01 +08:00 |
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3eeb01fe6f
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fix4
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2021-07-30 11:34:57 +08:00 |
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5f8e8a8c6a
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fix2
Co-authored-by: cxy004 <cxy004@qq.com>
|
2021-07-29 22:54:45 +08:00 |
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b33c1a2297
|
fix1
Co-authored-by: cxy004 <cxy004@qq.com>
Co-authored-by: Hooo1941 <Hooo1941@users.noreply.github.com>
|
2021-07-28 22:49:13 +08:00 |
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ebcd281f4b
|
datapath
Co-authored-by: cxy004 <cxy004@qq.com>
Co-authored-by: Hooo1941 <Hooo1941@users.noreply.github.com>
|
2021-07-28 16:39:10 +08:00 |
|
hoo
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d3a2d114b9
|
Pass MMU.
Co-authored-by: cxy004 <cxy004@qq.com>
Co-authored-by: Paul <1323564116@qq.com>
|
2021-07-22 19:26:31 +08:00 |
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1986765cfe
|
[resource] rename
|
2021-06-18 15:43:51 +08:00 |
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