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796c83b72a
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adjust mul/div
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2022-08-04 19:54:40 +08:00 |
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d31446ae87
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Configurable Cache & Bigger Cache
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2022-08-04 13:00:33 +08:00 |
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d487e8583d
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Update ENABLE_TLB
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2022-08-04 11:53:11 +08:00 |
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02f04a2bf3
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Update MU and DCache
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2022-08-03 14:26:44 +08:00 |
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db1aa1d615
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Manual Merge
Co-authored-by: cxy004 <cxy004@qq.com>
Co-authored-by: Hooo1941 <Hooo1941@users.noreply.github.com>
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2022-08-02 11:29:23 +08:00 |
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a7793c6741
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Another big update
1. refactor func test
2. fix CACHE inst
3. CP0 add Context Register
4. fix AXIWriter order
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2022-08-01 22:01:24 +08:00 |
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56cc2e5dcb
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fix: MU wstrb could directly passthrough
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2022-07-29 23:25:14 +08:00 |
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b25fbb5ee1
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fix: multiply model
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2022-07-29 18:48:58 +08:00 |
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bf7ee46645
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feat: reconfigure crossbar
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2022-07-29 18:26:27 +08:00 |
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7b33e4213a
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a big update
1. add test soft
2. modify verilator (TODO: crossbar need to replace)
3. fix CP0: now CU0 is always 1
4. Controller: cacheop
5. Controller: fix TEN
6. mycpu_top fix CP0_i
7. fix AXI.sv
8. fix AXIReader.sv
9. fix AXIWriter.sv: getting the correct data and length
10. MU: fix cache writeback, fix mem data mux, fix writer address, fix read request
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2022-07-29 18:25:58 +08:00 |
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4f7fe2adf2
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feat: MU rewrite 2
TLB Support
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2022-07-27 18:11:54 +08:00 |
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9ce588757d
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feat: MU rewrite 1
1. ALU format
2. FIX hazard (MOVN / MOVZ)
3. verilator support
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2022-07-27 15:07:16 +08:00 |
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