NSCSCC/MIPS
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fix k0

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Co-authored-by: cxy004 <cxy004@qq.com>
Co-authored-by: Hooo1941 <Hooo1941@users.noreply.github.com>
This commit is contained in:
Paul Pan 2021-07-30 15:46:51 +08:00
parent 0ad38a9a26
commit c487401438
2 changed files with 4 additions and 4 deletions
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6
src/MMU/MMU.sv
View File

@ -8,7 +8,7 @@ module MMU (
input clk, input clk,
rst, rst,
input logic [1:0] K0, input logic [2:0] K0,
ICache_i.mmu ic, ICache_i.mmu ic,
DCache_i.mmu dc, DCache_i.mmu dc,
@ -579,7 +579,7 @@ module MMU (
endmodule endmodule
module mapping ( module mapping (
input logic [1:0] K0, input logic [2:0] K0,
input word_t addr_in, input word_t addr_in,
output word_t addr_out, output word_t addr_out,
output logic cached output logic cached
@ -593,7 +593,7 @@ module mapping (
cached = 0; cached = 0;
end else begin // kseg0 -> CP0.K0 default: uncached end else begin // kseg0 -> CP0.K0 default: uncached
addr_out = addr_in & 32'h1FFF_FFFF; addr_out = addr_in & 32'h1FFF_FFFF;
cached = (K0 == 2'b11); cached = (K0 == 3'b011);
end end
end end
endmodule endmodule

2
src/MyCPU.sv
View File

@ -86,7 +86,7 @@ module mycpu_top (
word_t C0_wdata; word_t C0_wdata;
EXCEPTION_t C0_exception; EXCEPTION_t C0_exception;
word_t C0_EPC; word_t C0_EPC;
logic [3:0] K0; logic [2:0] K0;
AXI axi ( AXI axi (