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fix: multiply model

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This commit is contained in:
Paul Pan 2022-07-29 18:48:58 +08:00
parent bf7ee46645
commit b25fbb5ee1
4 changed files with 49 additions and 32 deletions
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47
resources/soft/func/start.S
View File

@ -316,20 +316,11 @@ inst_test:
jal wait_1s jal wait_1s
nop nop
# la t9, kseg0_kseg1 ##### la t9, kseg0_kseg1 #####
# jr t9 #kseg0 -> kseg1 jr t9 #kseg0 -> kseg1
# nop ##### nop #####
#
# kseg0_kseg1:
jal n6_lw_test #lw
nop
jal wait_1s
nop
jal n12_sw_test #sw
nop
jal wait_1s
nop
kseg0_kseg1:
jal n2_addu_test #addu jal n2_addu_test #addu
nop nop
@ -347,7 +338,10 @@ inst_test:
nop nop
jal wait_1s jal wait_1s
nop nop
jal n6_lw_test #lw
nop
jal wait_1s
nop
jal n7_or_test #or jal n7_or_test #or
nop nop
jal wait_1s jal wait_1s
@ -368,7 +362,10 @@ inst_test:
nop nop
jal wait_1s jal wait_1s
nop nop
jal n12_sw_test #sw
nop
jal wait_1s
nop
jal n13_j_test #j jal n13_j_test #j
nop nop
jal wait_1s jal wait_1s
@ -715,21 +712,21 @@ inst_test:
jal wait_1s jal wait_1s
nop nop
# la t1, n99_kseg1_kseg0 la t1, n99_kseg1_kseg0
# li t2, 0x20000000 li t2, 0x20000000
# subu t9, t1, t2 subu t9, t1, t2
# jr t9 jr t9
# nop nop
# n99_kseg1_kseg0: n99_kseg1_kseg0:
jal n99_cache_icache_test jal n99_cache_icache_test
nop nop
jal wait_1s jal wait_1s
nop nop
# la t9, n99_kseg0_kseg1 la t9, n99_kseg0_kseg1
# jr t9 jr t9
# nop nop
# n99_kseg0_kseg1: n99_kseg0_kseg1:
jal n100_movz_movn_test jal n100_movz_movn_test
nop nop

6
sim/Makefile
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@ -14,11 +14,11 @@ VERILATOR_BUILD_FLAGS += -cc --exe
# Generate makefile dependencies (not shown as complicates the Makefile) # Generate makefile dependencies (not shown as complicates the Makefile)
VERILATOR_BUILD_FLAGS += -MMD VERILATOR_BUILD_FLAGS += -MMD
# Optimize # Optimize
VERILATOR_BUILD_FLAGS += -O3 -x-assign 0 VERILATOR_BUILD_FLAGS += -O3 --x-assign fast --x-initial fast --no-threads
# Warn abount lint issues; may not want this on less solid designs # Warn abount lint issues; may not want this on less solid designs
VERILATOR_BUILD_FLAGS += -Wall VERILATOR_BUILD_FLAGS += -Wall
# Make waveforms # Make waveforms
VERILATOR_BUILD_FLAGS += --trace --trace-fst --trace-params --trace-structs --trace-threads 4 --trace-underscore VERILATOR_BUILD_FLAGS += --trace --trace-fst --trace-params --trace-structs --trace-underscore
# Check SystemVerilog assertions # Check SystemVerilog assertions
VERILATOR_BUILD_FLAGS += --assert VERILATOR_BUILD_FLAGS += --assert
# Generate coverage analysis # Generate coverage analysis
@ -27,7 +27,7 @@ VERILATOR_BUILD_FLAGS += --coverage
VERILATOR_BUILD_FLAGS += --build -j VERILATOR_BUILD_FLAGS += --build -j
# Simulation Defines # Simulation Defines
VERILATOR_FLAGS += -sv --stats --stats-vars -DSIMULATION_VERILATOR -DSIMULATION_PC VERILATOR_FLAGS += -sv -DSIMULATION_VERILATOR -DSIMULATION_PC
# Create annotated source # Create annotated source
VERILATOR_COV_FLAGS += --annotate logs/annotated VERILATOR_COV_FLAGS += --annotate logs/annotated

14
sim/model/mul_signed.sv
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@ -7,8 +7,18 @@ module mul_signed(
output logic [63:0] P output logic [63:0] P
); );
always_ff @(posedge CLK) logic [31:0] rA;
P <= $signed(A) * $signed(B); logic [31:0] rB;
logic [63:0] M[4:0];
always_ff @(posedge CLK) begin
rA <= A;
rB <= B;
M[0] <= $signed(rA) * $signed(rB);
for (integer i = 0; i < 4; i = i + 1)
M[i+1] <= M[i];
end
assign P = M[4];
endmodule endmodule

14
sim/model/mul_unsigned.sv
View File

@ -7,8 +7,18 @@ module mul_unsigned(
output logic [63:0] P output logic [63:0] P
); );
always_ff @(posedge CLK) logic [31:0] rA;
P <= $unsigned(A) * $unsigned(B); logic [31:0] rB;
logic [63:0] M[4:0];
always_ff @(posedge CLK) begin
rA <= A;
rB <= B;
M[0] <= $unsigned(rA) * $unsigned(rB);
for (integer i = 0; i < 4; i = i + 1)
M[i+1] <= M[i];
end
assign P = M[4];
endmodule endmodule