diff --git a/resources/soft/func/start.S b/resources/soft/func/start.S
index c53dfaf..ad8973e 100644
--- a/resources/soft/func/start.S
+++ b/resources/soft/func/start.S
@@ -316,20 +316,11 @@ inst_test:
     jal wait_1s
     nop
 
-#     la t9, kseg0_kseg1 #####
-#     jr t9              #kseg0 -> kseg1
-#     nop                #####
-# 
-# kseg0_kseg1:
-    jal n6_lw_test     #lw
-    nop
-    jal wait_1s
-    nop
-    jal n12_sw_test    #sw
-    nop
-    jal wait_1s
-    nop
+    la t9, kseg0_kseg1 #####
+    jr t9              #kseg0 -> kseg1
+    nop                #####
 
+kseg0_kseg1:
 
     jal n2_addu_test   #addu
     nop
@@ -347,7 +338,10 @@ inst_test:
     nop
     jal wait_1s
     nop
-
+    jal n6_lw_test     #lw
+    nop
+    jal wait_1s
+    nop
     jal n7_or_test     #or
     nop
     jal wait_1s
@@ -368,7 +362,10 @@ inst_test:
     nop
     jal wait_1s
     nop
-
+    jal n12_sw_test    #sw
+    nop
+    jal wait_1s
+    nop
     jal n13_j_test       #j
     nop
     jal wait_1s
@@ -715,21 +712,21 @@ inst_test:
     jal wait_1s
     nop
 
-#     la t1, n99_kseg1_kseg0
-#     li t2, 0x20000000
-#     subu t9, t1, t2
-#     jr t9
-#     nop
-# n99_kseg1_kseg0:
+    la t1, n99_kseg1_kseg0
+    li t2, 0x20000000
+    subu t9, t1, t2
+    jr t9
+    nop
+n99_kseg1_kseg0:
     jal n99_cache_icache_test
     nop
     jal wait_1s
     nop
 
-#     la t9, n99_kseg0_kseg1
-#     jr t9
-#     nop
-# n99_kseg0_kseg1:
+    la t9, n99_kseg0_kseg1
+    jr t9
+    nop
+n99_kseg0_kseg1:
     
     jal n100_movz_movn_test
     nop
diff --git a/sim/Makefile b/sim/Makefile
index b0c1c32..3824c8b 100644
--- a/sim/Makefile
+++ b/sim/Makefile
@@ -14,11 +14,11 @@ VERILATOR_BUILD_FLAGS += -cc --exe
 # Generate makefile dependencies (not shown as complicates the Makefile)
 VERILATOR_BUILD_FLAGS += -MMD
 # Optimize
-VERILATOR_BUILD_FLAGS += -O3 -x-assign 0
+VERILATOR_BUILD_FLAGS += -O3 --x-assign fast --x-initial fast --no-threads
 # Warn abount lint issues; may not want this on less solid designs
 VERILATOR_BUILD_FLAGS += -Wall
 # Make waveforms
-VERILATOR_BUILD_FLAGS += --trace --trace-fst --trace-params --trace-structs --trace-threads 4 --trace-underscore
+VERILATOR_BUILD_FLAGS += --trace --trace-fst --trace-params --trace-structs --trace-underscore
 # Check SystemVerilog assertions
 VERILATOR_BUILD_FLAGS += --assert
 # Generate coverage analysis
@@ -27,7 +27,7 @@ VERILATOR_BUILD_FLAGS += --coverage
 VERILATOR_BUILD_FLAGS += --build -j
 
 # Simulation Defines
-VERILATOR_FLAGS += -sv --stats --stats-vars -DSIMULATION_VERILATOR -DSIMULATION_PC
+VERILATOR_FLAGS += -sv -DSIMULATION_VERILATOR -DSIMULATION_PC
 
 # Create annotated source
 VERILATOR_COV_FLAGS += --annotate logs/annotated
diff --git a/sim/model/mul_signed.sv b/sim/model/mul_signed.sv
index 135703e..5b62f38 100644
--- a/sim/model/mul_signed.sv
+++ b/sim/model/mul_signed.sv
@@ -7,8 +7,18 @@ module mul_signed(
   output logic [63:0] P
 );
 
-  always_ff @(posedge CLK)
-    P <= $signed(A) * $signed(B);
+  logic [31:0] rA;
+  logic [31:0] rB;
+  logic [63:0] M[4:0];
 
+  always_ff @(posedge CLK) begin
+    rA   <= A;
+    rB   <= B;
+    M[0] <= $signed(rA) * $signed(rB);
+    for (integer i = 0; i < 4; i = i + 1)
+      M[i+1] <= M[i];
+  end
+
+  assign P = M[4];
 
 endmodule
diff --git a/sim/model/mul_unsigned.sv b/sim/model/mul_unsigned.sv
index 6bc3082..8a3afd4 100644
--- a/sim/model/mul_unsigned.sv
+++ b/sim/model/mul_unsigned.sv
@@ -7,8 +7,18 @@ module mul_unsigned(
   output logic [63:0] P
 );
 
-  always_ff @(posedge CLK)
-    P <= $unsigned(A) * $unsigned(B);
+  logic [31:0] rA;
+  logic [31:0] rB;
+  logic [63:0] M[4:0];
 
+  always_ff @(posedge CLK) begin
+    rA   <= A;
+    rB   <= B;
+    M[0] <= $unsigned(rA) * $unsigned(rB);
+    for (integer i = 0; i < 4; i = i + 1)
+      M[i+1] <= M[i];
+  end
+
+  assign P = M[4];
 
 endmodule