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fix: arch: riscv: trap: {get, set}_reg are shifted with wrong offset

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Paul Pan 2024-06-16 00:20:56 +08:00
parent 797652c2b8
commit c066097c82
1 changed files with 5 additions and 5 deletions
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10
kernel/src/arch/riscv/trap.rs
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@ -110,16 +110,16 @@ impl TrapContextOps for TrapContext {
} }
fn get_reg(&self, index: usize) -> usize { fn get_reg(&self, index: usize) -> usize {
// x10 ~ x17: Function arguments // x9(a0) ~ x16(a7): Function arguments
assert!(index < 8, "TrapContext get_reg index out of range"); assert!(index < 8, "TrapContext get_reg index out of range");
self.gprs[index + 10] self.gprs[index + 9]
} }
fn set_reg(&mut self, index: usize, value: usize) { fn set_reg(&mut self, index: usize, value: usize) {
// x10 ~ x17: Function arguments // x9(a0) ~ x16(a7): Function arguments
// x10 ~ x11: Function return values // x9(a0) ~ x10(a1): Function return values
assert!(index < 8, "TrapContext set_reg index out of range"); assert!(index < 8, "TrapContext set_reg index out of range");
self.gprs[index + 10] = value; self.gprs[index + 9] = value;
} }
} }