From c066097c82be6d07148c6dbad727d57d0fa05c9d Mon Sep 17 00:00:00 2001 From: Paul Pan Date: Sun, 16 Jun 2024 00:20:56 +0800 Subject: [PATCH] fix: arch: riscv: trap: {get, set}_reg are shifted with wrong offset --- kernel/src/arch/riscv/trap.rs | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/kernel/src/arch/riscv/trap.rs b/kernel/src/arch/riscv/trap.rs index c836e62..78dbf6d 100644 --- a/kernel/src/arch/riscv/trap.rs +++ b/kernel/src/arch/riscv/trap.rs @@ -110,16 +110,16 @@ impl TrapContextOps for TrapContext { } fn get_reg(&self, index: usize) -> usize { - // x10 ~ x17: Function arguments + // x9(a0) ~ x16(a7): Function arguments assert!(index < 8, "TrapContext get_reg index out of range"); - self.gprs[index + 10] + self.gprs[index + 9] } fn set_reg(&mut self, index: usize, value: usize) { - // x10 ~ x17: Function arguments - // x10 ~ x11: Function return values + // x9(a0) ~ x16(a7): Function arguments + // x9(a0) ~ x10(a1): Function return values assert!(index < 8, "TrapContext set_reg index out of range"); - self.gprs[index + 10] = value; + self.gprs[index + 9] = value; } }