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chore: kernel/arch/riscv/trap: also log sp

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This commit is contained in:
Paul Pan 2024-08-23 20:45:08 +08:00
parent 917629f16e
commit 6bbc889d7f
3 changed files with 34 additions and 17 deletions
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2
kernel/Cargo.toml
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@ -39,4 +39,4 @@ uart_16550 = "0.3"
[target.'cfg(target_arch = "riscv64")'.dependencies] [target.'cfg(target_arch = "riscv64")'.dependencies]
riscv = { version = "0.11", features = ["s-mode"] } riscv = { version = "0.11", features = ["s-mode"] }
sbi-rt = { version = "0.0" } sbi-rt = { version = "0.0.3" }

19
kernel/src/arch/riscv/backtrace.rs
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@ -2,19 +2,28 @@ use super::layout::{BSS_END, BSS_START, TEXT_END, TEXT_START};
use crate::plat::backtrace::FrameWalker; use crate::plat::backtrace::FrameWalker;
use utils::addr::{AddressOps, VirtAddr}; use utils::addr::{AddressOps, VirtAddr};
impl FrameWalker { #[inline]
fn read_fp() -> usize { pub fn read_fp() -> usize {
let fp; let fp;
unsafe { core::arch::asm!("mv {}, fp", out(reg) fp) } unsafe { core::arch::asm!("mv {}, fp", out(reg) fp) }
fp fp
} }
fn read_ra() -> usize { #[inline]
pub fn read_sp() -> usize {
let sp;
unsafe { core::arch::asm!("mv {}, sp", out(reg) sp) }
sp
}
#[inline]
pub fn read_ra() -> usize {
let ra; let ra;
unsafe { core::arch::asm!("mv {}, ra", out(reg) ra) } unsafe { core::arch::asm!("mv {}, ra", out(reg) ra) }
ra ra
} }
impl FrameWalker {
fn is_valid(&self) -> bool { fn is_valid(&self) -> bool {
let fp_valid = unsafe { BSS_START.as_virt_addr() <= self.current_fp && self.current_fp < BSS_END.as_virt_addr() }; let fp_valid = unsafe { BSS_START.as_virt_addr() <= self.current_fp && self.current_fp < BSS_END.as_virt_addr() };
let pc_valid = unsafe { TEXT_START.as_virt_addr() <= self.current_pc && self.current_pc < TEXT_END.as_virt_addr() }; let pc_valid = unsafe { TEXT_START.as_virt_addr() <= self.current_pc && self.current_pc < TEXT_END.as_virt_addr() };
@ -28,8 +37,8 @@ impl FrameWalker {
pub fn new() -> Self { pub fn new() -> Self {
// current_{fp, pc} is deliberately missed for printing // current_{fp, pc} is deliberately missed for printing
Self { Self {
current_fp: VirtAddr::from(FrameWalker::read_fp()), current_fp: VirtAddr::from(read_fp()),
current_pc: VirtAddr::from(FrameWalker::read_ra()), current_pc: VirtAddr::from(read_ra()),
} }
} }
} }

12
kernel/src/arch/riscv/trap.rs
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@ -1,3 +1,4 @@
use crate::arch::riscv::backtrace::read_sp;
use crate::entry::HART_ID; use crate::entry::HART_ID;
use crate::objects::*; use crate::objects::*;
use crate::plat::console::CONSOLE; use crate::plat::console::CONSOLE;
@ -55,12 +56,19 @@ impl TrapContextOps for TrapContext {
fn configure_idle_thread(&mut self) { fn configure_idle_thread(&mut self) {
self.sepc = idle_thread as usize; self.sepc = idle_thread as usize;
self.sstatus = (1 << 5) | (1 << 8); // SPIE + SPP self.sstatus = (1 << 5) // SPIE: enable interrupt in idle thread
| (1 << 8) // SPP: run in kernel mode in idle thread
;
} }
fn handle_trap(&mut self, from_kernel: bool) { fn handle_trap(&mut self, from_kernel: bool) {
let scause = riscv::register::scause::read(); let scause = riscv::register::scause::read();
trace!("[Trap] cpu@{} scause: {:?}", HART_ID.get(), scause.cause()); trace!(
"[Trap] cpu@{} scause: {:?} sp: {:#x}",
HART_ID.get(),
scause.cause(),
read_sp()
);
macro_rules! panic_fatal { macro_rules! panic_fatal {
($msg:expr) => { ($msg:expr) => {