mirror of
https://github.com/panpaul/tiny_os
synced 2024-09-20 09:45:19 +08:00
feat: drop riscv32
This commit is contained in:
parent
1d672b4ff8
commit
32759ef037
@ -6,22 +6,18 @@ edition = "2021"
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# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
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# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
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[features]
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[features]
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default = ["riscv.board.virt", "riscv.riscv64"]
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default = ["riscv.board.virt"]
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legacy = ["utils/legacy", "vspace/legacy"]
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riscv = []
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riscv = []
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"riscv.pagetable.sv32" = []
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"riscv.pagetable.sv39" = []
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"riscv.pagetable.sv39" = []
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"riscv.pagetable.sv48" = []
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"riscv.pagetable.sv48" = []
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"riscv.pagetable.sv57" = []
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"riscv.pagetable.sv57" = []
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"riscv.riscv64" = ["riscv", "riscv.pagetable.sv39"]
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"riscv.riscv64" = ["riscv", "riscv.pagetable.sv39"]
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"riscv.riscv32" = ["riscv", "riscv.pagetable.sv32", "legacy"]
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"riscv.board.default" = []
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"riscv.board.default" = ["riscv.riscv64"]
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"riscv.board.virt" = []
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"riscv.board.virt" = ["riscv.riscv64"]
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[dependencies]
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[dependencies]
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allocator = { path = "../lib/allocator" }
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allocator = { path = "../lib/allocator" }
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@ -39,6 +35,6 @@ spin = "0.9"
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static_assertions = "1.1"
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static_assertions = "1.1"
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uart_16550 = "0.3"
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uart_16550 = "0.3"
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[target.'cfg(any(target_arch = "riscv32", target_arch = "riscv64"))'.dependencies]
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[target.'cfg(target_arch = "riscv64")'.dependencies]
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riscv = { version = "0.11", features = ["s-mode"] }
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riscv = { version = "0.11", features = ["s-mode"] }
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sbi-rt = { version = "0.0" }
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sbi-rt = { version = "0.0" }
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@ -1,41 +1,31 @@
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use cfg_if::cfg_if;
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use core::arch::global_asm;
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use core::arch::global_asm;
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cfg_if! {
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global_asm!(
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if #[cfg(target_arch = "riscv32")] {
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"
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global_asm!("
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.section .text
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.section .text
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.global boot_setup_early_paging
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boot_setup_early_paging:
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boot_setup_early_paging:
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jr ra
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lla t1, boot_page_table
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"
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srli t1, t1, 12
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);
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li t2, 8 << 60
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} else if #[cfg(target_arch = "riscv64")]{
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or t1, t1, t2
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global_asm!("
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csrw satp, t1
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.section .text
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sfence.vma
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boot_setup_early_paging:
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jr ra
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lla t1, boot_page_table
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srli t1, t1, 12
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.section .temp.boot_page_table
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li t2, 8 << 60
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.align 12
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or t1, t1, t2
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boot_page_table:
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csrw satp, t1
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# sv39 page table
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sfence.vma
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# 0x00000000_00000000 -> 0x00000000 [ 0x00000000_00000000 -> 0x00000000_40000000 ]
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jr ra
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# 0x00000000_40000000 -> 0x40000000 [ 0x00000000_40000000 -> 0x00000000_80000000 ]
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# 0x00000000_80000000 -> 0x80000000 [ 0x00000000_80000000 -> 0x00000001_00000000 ]
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.section .temp.boot_page_table
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# 0xFFFFFFD0_00000000 -> 0x80000000 [ 0xFFFFFFD0_00000000 -> 0xFFFFFFD0_40000000 ]
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.align 12
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.quad (0x00000 << 10) | 0xf
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boot_page_table:
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.quad (0x40000 << 10) | 0xf
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# sv39 page table
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.quad (0x80000 << 10) | 0xf
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# 0x00000000_00000000 -> 0x00000000 [ 0x00000000_00000000 -> 0x00000000_40000000 ]
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.zero 8 * 317
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# 0x00000000_40000000 -> 0x40000000 [ 0x00000000_40000000 -> 0x00000000_80000000 ]
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.quad (0x80000 << 10) | 0xf
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# 0x00000000_80000000 -> 0x80000000 [ 0x00000000_80000000 -> 0x00000001_00000000 ]
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.zero 8 * 191
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# 0xFFFFFFD0_00000000 -> 0x80000000 [ 0xFFFFFFD0_00000000 -> 0xFFFFFFD0_40000000 ]
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"
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.quad (0x00000 << 10) | 0xf
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);
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.quad (0x40000 << 10) | 0xf
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.quad (0x80000 << 10) | 0xf
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.zero 8 * 317
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.quad (0x80000 << 10) | 0xf
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.zero 8 * 191
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"
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);
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}
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}
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@ -1,5 +1,5 @@
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use crate::arch::init_early_console;
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use crate::arch::init_early_console;
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use crate::arch::layout::{mmap_phys_to_virt, zero_bss};
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use crate::arch::layout::{mmap_phys_to_virt, zero_bss, KERNEL_OFFSET};
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use crate::arch::vspace::{setup_kernel_paging, setup_memory};
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use crate::arch::vspace::{setup_kernel_paging, setup_memory};
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use crate::entry::{rust_main, HART_ID};
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use crate::entry::{rust_main, HART_ID};
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use crate::plat::console::mute_console;
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use crate::plat::console::mute_console;
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@ -39,14 +39,8 @@ unsafe extern "C" fn _start(hart_id: usize, device_tree_addr: usize) -> ! {
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add tp, tp, t0
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add tp, tp, t0
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add sp, sp, t0
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add sp, sp, t0
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# TODO: riscv32 do not need it, add a function in board/ and call it
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# setup early paging
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# setup early paging
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lla t1, boot_page_table
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call boot_setup_early_paging
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srli t1, t1, 12
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li t2, 8 << 60
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or t1, t1, t2
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csrw satp, t1
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sfence.vma
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# jump to absolute address
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# jump to absolute address
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lla t1, {main}
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lla t1, {main}
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@ -58,22 +52,6 @@ unsafe extern "C" fn _start(hart_id: usize, device_tree_addr: usize) -> ! {
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KERNEL_OFFSET: .quad __kernel_offset
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KERNEL_OFFSET: .quad __kernel_offset
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.global MMAP_OFFSET
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.global MMAP_OFFSET
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MMAP_OFFSET: .quad MMAP_BASE_ADDRESS
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MMAP_OFFSET: .quad MMAP_BASE_ADDRESS
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# TODO: move this into board/
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.section .temp.boot_page_table
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.align 12
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boot_page_table:
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# sv39 page table
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# 0x00000000_00000000 -> 0x00000000 [ 0x00000000_00000000 -> 0x00000000_40000000 ]
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# 0x00000000_40000000 -> 0x40000000 [ 0x00000000_40000000 -> 0x00000000_80000000 ]
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# 0x00000000_80000000 -> 0x80000000 [ 0x00000000_80000000 -> 0x00000001_00000000 ]
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# 0xFFFFFFD0_00000000 -> 0x80000000 [ 0xFFFFFFD0_00000000 -> 0xFFFFFFD0_40000000 ]
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.quad (0x00000 << 10) | 0xf
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.quad (0x40000 << 10) | 0xf
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.quad (0x80000 << 10) | 0xf
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.zero 8 * 317
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.quad (0x80000 << 10) | 0xf
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.zero 8 * 191
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",
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",
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stack_size = const STACK_SIZE,
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stack_size = const STACK_SIZE,
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stack = sym STACK,
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stack = sym STACK,
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@ -8,14 +8,7 @@ use riscv::register::stvec::TrapMode;
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use crate::plat::timer::{Timer, TimerOps};
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use crate::plat::timer::{Timer, TimerOps};
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use crate::plat::trap::{Trap, TrapContextOps, TrapOps};
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use crate::plat::trap::{Trap, TrapContextOps, TrapOps};
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cfg_if! {
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core::arch::global_asm!(include_str!("./asm/trap64.S"));
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if #[cfg(feature = "riscv.riscv64")] {
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core::arch::global_asm!(include_str!("./asm/trap64.S"));
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} else if #[cfg(feature = "riscv.riscv32")] {
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core::arch::global_asm!(include_str!("./asm/trap32.S"));
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}
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}
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core::arch::global_asm!(include_str!("./asm/trap_common.S"));
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core::arch::global_asm!(include_str!("./asm/trap_common.S"));
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extern "C" {
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extern "C" {
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@ -73,12 +73,8 @@ impl From<MapAttr> for PTEFlags {
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}
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}
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}
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}
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#[cfg(not(feature = "riscv.pagetable.sv32"))]
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assert_eq_size!(Entry, u64);
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assert_eq_size!(Entry, u64);
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#[cfg(feature = "riscv.pagetable.sv32")]
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assert_eq_size!(Entry, u32);
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#[derive(Clone, Copy, Default)]
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#[derive(Clone, Copy, Default)]
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pub struct Entry(usize);
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pub struct Entry(usize);
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@ -32,8 +32,6 @@ impl Table {
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}
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}
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pub fn mode() -> riscv::register::satp::Mode {
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pub fn mode() -> riscv::register::satp::Mode {
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#[cfg(feature = "riscv.pagetable.sv32")]
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return riscv::register::satp::Mode::Sv32;
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#[cfg(feature = "riscv.pagetable.sv39")]
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#[cfg(feature = "riscv.pagetable.sv39")]
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return riscv::register::satp::Mode::Sv39;
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return riscv::register::satp::Mode::Sv39;
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#[cfg(feature = "riscv.pagetable.sv48")]
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#[cfg(feature = "riscv.pagetable.sv48")]
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@ -46,8 +44,6 @@ impl Table {
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impl TableOps for Table {
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impl TableOps for Table {
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type Entry = Entry;
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type Entry = Entry;
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#[cfg(feature = "riscv.pagetable.sv32")]
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const MAX_PAGE_SIZE: TableLevel = TableLevel::Level1;
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#[cfg(feature = "riscv.pagetable.sv39")]
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#[cfg(feature = "riscv.pagetable.sv39")]
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const MAX_PAGE_SIZE: TableLevel = TableLevel::Level2;
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const MAX_PAGE_SIZE: TableLevel = TableLevel::Level2;
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@ -34,13 +34,6 @@ pub trait PhysAddrPaging {
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}
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}
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}
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}
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#[cfg(feature = "riscv.pagetable.sv32")]
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impl PhysAddrPaging for PhysAddr {
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const PG_OFFSET: usize = 12;
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const PPN_BITS: usize = 22;
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const PPN_OFFSET: usize = 10;
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}
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#[cfg(feature = "riscv.pagetable.sv39")]
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#[cfg(feature = "riscv.pagetable.sv39")]
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impl PhysAddrPaging for PhysAddr {
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impl PhysAddrPaging for PhysAddr {
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const PG_OFFSET: usize = 12;
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const PG_OFFSET: usize = 12;
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@ -72,12 +65,6 @@ pub trait VirtAddrPaging {
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}
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}
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}
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}
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#[cfg(feature = "riscv.pagetable.sv32")]
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impl VirtAddrPaging for VirtAddr {
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const PG_OFFSET: usize = 12;
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const VPN_BITS: usize = 10;
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}
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#[cfg(feature = "riscv.pagetable.sv39")]
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#[cfg(feature = "riscv.pagetable.sv39")]
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impl VirtAddrPaging for VirtAddr {
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impl VirtAddrPaging for VirtAddr {
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const PG_OFFSET: usize = 12;
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const PG_OFFSET: usize = 12;
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@ -98,14 +85,9 @@ impl TableLevelSize for TableLevel {
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fn level_size(&self) -> usize {
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fn level_size(&self) -> usize {
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match self {
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match self {
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Self::Level0 => 4 * KIB,
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Self::Level0 => 4 * KIB,
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#[cfg(feature = "riscv.pagetable.sv32")]
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Self::Level1 => 4 * MIB,
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#[cfg(not(feature = "riscv.pagetable.sv32"))]
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Self::Level1 => 2 * MIB,
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Self::Level1 => 2 * MIB,
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Self::Level2 => 1 * GIB,
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Self::Level2 => 1 * GIB,
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#[cfg(not(feature = "legacy"))]
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Self::Level3 => 512 * GIB,
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Self::Level3 => 512 * GIB,
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#[cfg(not(feature = "legacy"))]
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Self::Level4 => 256 * TIB,
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Self::Level4 => 256 * TIB,
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}
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}
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}
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}
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@ -7,9 +7,7 @@ pub enum TableLevel {
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Level0 = 0, // KiloPage
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Level0 = 0, // KiloPage
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Level1 = 1, // MegaPage
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Level1 = 1, // MegaPage
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Level2 = 2, // GigaPage
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Level2 = 2, // GigaPage
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#[cfg(not(feature = "legacy"))]
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Level3 = 3, // TeraPage
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Level3 = 3, // TeraPage
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#[cfg(not(feature = "legacy"))]
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Level4 = 4, // PetaPage
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Level4 = 4, // PetaPage
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}
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}
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@ -19,9 +17,7 @@ impl TableLevel {
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Self::Level0 => None,
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Self::Level0 => None,
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Self::Level1 => Some(Self::Level0),
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Self::Level1 => Some(Self::Level0),
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Self::Level2 => Some(Self::Level1),
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Self::Level2 => Some(Self::Level1),
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#[cfg(not(feature = "legacy"))]
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Self::Level3 => Some(Self::Level2),
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Self::Level3 => Some(Self::Level2),
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#[cfg(not(feature = "legacy"))]
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Self::Level4 => Some(Self::Level3),
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Self::Level4 => Some(Self::Level3),
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}
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}
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}
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}
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@ -31,9 +27,7 @@ impl TableLevel {
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Self::Level0 => Some(Self::Level1),
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Self::Level0 => Some(Self::Level1),
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Self::Level1 => Some(Self::Level2),
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Self::Level1 => Some(Self::Level2),
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Self::Level2 => Some(Self::Level3),
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Self::Level2 => Some(Self::Level3),
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#[cfg(not(feature = "legacy"))]
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Self::Level3 => Some(Self::Level4),
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Self::Level3 => Some(Self::Level4),
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#[cfg(not(feature = "legacy"))]
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Self::Level4 => None,
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Self::Level4 => None,
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}
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}
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}
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}
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@ -11,7 +11,6 @@ pub enum Profile {
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#[derive(ValueEnum, Copy, Clone)]
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#[derive(ValueEnum, Copy, Clone)]
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#[value(rename_all = "snake_case")]
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#[value(rename_all = "snake_case")]
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pub enum Arch {
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pub enum Arch {
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RISCV32,
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RISCV64,
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RISCV64,
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}
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}
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@ -32,8 +31,8 @@ impl Arch {
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pub fn rust_flags(&self) -> Vec<String> {
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pub fn rust_flags(&self) -> Vec<String> {
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let mut flags = Self::FLAGS_RELOCATION.iter().map(|s| s.to_string()).collect::<Vec<_>>();
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let mut flags = Self::FLAGS_RELOCATION.iter().map(|s| s.to_string()).collect::<Vec<_>>();
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match self {
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match self {
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Arch::RISCV32 | Arch::RISCV64 => {
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Arch::RISCV64 => {
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flags.push(format!("-Clink-arg=-Tkernel/src/arch/riscv/linker{}.ld", self.bits()));
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flags.push("-Clink-arg=-Tkernel/src/arch/riscv/linker64.ld".to_string());
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flags
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flags
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},
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},
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}
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}
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@ -41,13 +40,12 @@ impl Arch {
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pub fn triple(&self) -> String {
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pub fn triple(&self) -> String {
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match self {
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match self {
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Arch::RISCV32 | Arch::RISCV64 => format!("riscv{}imac-unknown-none-elf", self.bits()),
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Arch::RISCV64 => "riscv64imac-unknown-none-elf".to_string(),
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}
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}
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}
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}
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pub fn bits(&self) -> u32 {
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pub fn bits(&self) -> u32 {
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match self {
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match self {
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Arch::RISCV32 => 32,
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Arch::RISCV64 => 64,
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Arch::RISCV64 => 64,
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}
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}
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}
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}
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