diff --git a/kernel/Cargo.toml b/kernel/Cargo.toml index 9ac2d44..7d5f8b9 100644 --- a/kernel/Cargo.toml +++ b/kernel/Cargo.toml @@ -6,22 +6,18 @@ edition = "2021" # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html [features] -default = ["riscv.board.virt", "riscv.riscv64"] - -legacy = ["utils/legacy", "vspace/legacy"] +default = ["riscv.board.virt"] riscv = [] -"riscv.pagetable.sv32" = [] "riscv.pagetable.sv39" = [] "riscv.pagetable.sv48" = [] "riscv.pagetable.sv57" = [] "riscv.riscv64" = ["riscv", "riscv.pagetable.sv39"] -"riscv.riscv32" = ["riscv", "riscv.pagetable.sv32", "legacy"] -"riscv.board.default" = [] -"riscv.board.virt" = [] +"riscv.board.default" = ["riscv.riscv64"] +"riscv.board.virt" = ["riscv.riscv64"] [dependencies] allocator = { path = "../lib/allocator" } @@ -39,6 +35,6 @@ spin = "0.9" static_assertions = "1.1" uart_16550 = "0.3" -[target.'cfg(any(target_arch = "riscv32", target_arch = "riscv64"))'.dependencies] +[target.'cfg(target_arch = "riscv64")'.dependencies] riscv = { version = "0.11", features = ["s-mode"] } sbi-rt = { version = "0.0" } diff --git a/kernel/src/arch/riscv/board/default/boot.rs b/kernel/src/arch/riscv/board/default/boot.rs index a1725c3..7764c9d 100644 --- a/kernel/src/arch/riscv/board/default/boot.rs +++ b/kernel/src/arch/riscv/board/default/boot.rs @@ -1,41 +1,31 @@ -use cfg_if::cfg_if; use core::arch::global_asm; -cfg_if! { - if #[cfg(target_arch = "riscv32")] { - global_asm!(" - .section .text - boot_setup_early_paging: - jr ra - " - ); - } else if #[cfg(target_arch = "riscv64")]{ - global_asm!(" - .section .text - boot_setup_early_paging: - lla t1, boot_page_table - srli t1, t1, 12 - li t2, 8 << 60 - or t1, t1, t2 - csrw satp, t1 - sfence.vma - jr ra - - .section .temp.boot_page_table - .align 12 - boot_page_table: - # sv39 page table - # 0x00000000_00000000 -> 0x00000000 [ 0x00000000_00000000 -> 0x00000000_40000000 ] - # 0x00000000_40000000 -> 0x40000000 [ 0x00000000_40000000 -> 0x00000000_80000000 ] - # 0x00000000_80000000 -> 0x80000000 [ 0x00000000_80000000 -> 0x00000001_00000000 ] - # 0xFFFFFFD0_00000000 -> 0x80000000 [ 0xFFFFFFD0_00000000 -> 0xFFFFFFD0_40000000 ] - .quad (0x00000 << 10) | 0xf - .quad (0x40000 << 10) | 0xf - .quad (0x80000 << 10) | 0xf - .zero 8 * 317 - .quad (0x80000 << 10) | 0xf - .zero 8 * 191 - " - ); - } -} +global_asm!( + " + .section .text + .global boot_setup_early_paging + boot_setup_early_paging: + lla t1, boot_page_table + srli t1, t1, 12 + li t2, 8 << 60 + or t1, t1, t2 + csrw satp, t1 + sfence.vma + jr ra + + .section .temp.boot_page_table + .align 12 + boot_page_table: + # sv39 page table + # 0x00000000_00000000 -> 0x00000000 [ 0x00000000_00000000 -> 0x00000000_40000000 ] + # 0x00000000_40000000 -> 0x40000000 [ 0x00000000_40000000 -> 0x00000000_80000000 ] + # 0x00000000_80000000 -> 0x80000000 [ 0x00000000_80000000 -> 0x00000001_00000000 ] + # 0xFFFFFFD0_00000000 -> 0x80000000 [ 0xFFFFFFD0_00000000 -> 0xFFFFFFD0_40000000 ] + .quad (0x00000 << 10) | 0xf + .quad (0x40000 << 10) | 0xf + .quad (0x80000 << 10) | 0xf + .zero 8 * 317 + .quad (0x80000 << 10) | 0xf + .zero 8 * 191 + " +); diff --git a/kernel/src/arch/riscv/entry.rs b/kernel/src/arch/riscv/entry.rs index 4c4bb0c..c98e363 100644 --- a/kernel/src/arch/riscv/entry.rs +++ b/kernel/src/arch/riscv/entry.rs @@ -1,5 +1,5 @@ use crate::arch::init_early_console; -use crate::arch::layout::{mmap_phys_to_virt, zero_bss}; +use crate::arch::layout::{mmap_phys_to_virt, zero_bss, KERNEL_OFFSET}; use crate::arch::vspace::{setup_kernel_paging, setup_memory}; use crate::entry::{rust_main, HART_ID}; use crate::plat::console::mute_console; @@ -39,14 +39,8 @@ unsafe extern "C" fn _start(hart_id: usize, device_tree_addr: usize) -> ! { add tp, tp, t0 add sp, sp, t0 - # TODO: riscv32 do not need it, add a function in board/ and call it # setup early paging - lla t1, boot_page_table - srli t1, t1, 12 - li t2, 8 << 60 - or t1, t1, t2 - csrw satp, t1 - sfence.vma + call boot_setup_early_paging # jump to absolute address lla t1, {main} @@ -58,22 +52,6 @@ unsafe extern "C" fn _start(hart_id: usize, device_tree_addr: usize) -> ! { KERNEL_OFFSET: .quad __kernel_offset .global MMAP_OFFSET MMAP_OFFSET: .quad MMAP_BASE_ADDRESS - - # TODO: move this into board/ - .section .temp.boot_page_table - .align 12 - boot_page_table: - # sv39 page table - # 0x00000000_00000000 -> 0x00000000 [ 0x00000000_00000000 -> 0x00000000_40000000 ] - # 0x00000000_40000000 -> 0x40000000 [ 0x00000000_40000000 -> 0x00000000_80000000 ] - # 0x00000000_80000000 -> 0x80000000 [ 0x00000000_80000000 -> 0x00000001_00000000 ] - # 0xFFFFFFD0_00000000 -> 0x80000000 [ 0xFFFFFFD0_00000000 -> 0xFFFFFFD0_40000000 ] - .quad (0x00000 << 10) | 0xf - .quad (0x40000 << 10) | 0xf - .quad (0x80000 << 10) | 0xf - .zero 8 * 317 - .quad (0x80000 << 10) | 0xf - .zero 8 * 191 ", stack_size = const STACK_SIZE, stack = sym STACK, diff --git a/kernel/src/arch/riscv/trap.rs b/kernel/src/arch/riscv/trap.rs index cd80201..1c21ee3 100644 --- a/kernel/src/arch/riscv/trap.rs +++ b/kernel/src/arch/riscv/trap.rs @@ -8,14 +8,7 @@ use riscv::register::stvec::TrapMode; use crate::plat::timer::{Timer, TimerOps}; use crate::plat::trap::{Trap, TrapContextOps, TrapOps}; -cfg_if! { - if #[cfg(feature = "riscv.riscv64")] { - core::arch::global_asm!(include_str!("./asm/trap64.S")); - } else if #[cfg(feature = "riscv.riscv32")] { - core::arch::global_asm!(include_str!("./asm/trap32.S")); - } -} - +core::arch::global_asm!(include_str!("./asm/trap64.S")); core::arch::global_asm!(include_str!("./asm/trap_common.S")); extern "C" { diff --git a/kernel/src/arch/riscv/vspace/entry.rs b/kernel/src/arch/riscv/vspace/entry.rs index c3bb8d1..2dba018 100644 --- a/kernel/src/arch/riscv/vspace/entry.rs +++ b/kernel/src/arch/riscv/vspace/entry.rs @@ -73,12 +73,8 @@ impl From for PTEFlags { } } -#[cfg(not(feature = "riscv.pagetable.sv32"))] assert_eq_size!(Entry, u64); -#[cfg(feature = "riscv.pagetable.sv32")] -assert_eq_size!(Entry, u32); - #[derive(Clone, Copy, Default)] pub struct Entry(usize); diff --git a/kernel/src/arch/riscv/vspace/table.rs b/kernel/src/arch/riscv/vspace/table.rs index bef8a18..397c6a8 100644 --- a/kernel/src/arch/riscv/vspace/table.rs +++ b/kernel/src/arch/riscv/vspace/table.rs @@ -32,8 +32,6 @@ impl Table { } pub fn mode() -> riscv::register::satp::Mode { - #[cfg(feature = "riscv.pagetable.sv32")] - return riscv::register::satp::Mode::Sv32; #[cfg(feature = "riscv.pagetable.sv39")] return riscv::register::satp::Mode::Sv39; #[cfg(feature = "riscv.pagetable.sv48")] @@ -46,8 +44,6 @@ impl Table { impl TableOps for Table { type Entry = Entry; - #[cfg(feature = "riscv.pagetable.sv32")] - const MAX_PAGE_SIZE: TableLevel = TableLevel::Level1; #[cfg(feature = "riscv.pagetable.sv39")] const MAX_PAGE_SIZE: TableLevel = TableLevel::Level2; diff --git a/kernel/src/arch/riscv/vspace/traits.rs b/kernel/src/arch/riscv/vspace/traits.rs index 3d7c112..adc0421 100644 --- a/kernel/src/arch/riscv/vspace/traits.rs +++ b/kernel/src/arch/riscv/vspace/traits.rs @@ -34,13 +34,6 @@ pub trait PhysAddrPaging { } } -#[cfg(feature = "riscv.pagetable.sv32")] -impl PhysAddrPaging for PhysAddr { - const PG_OFFSET: usize = 12; - const PPN_BITS: usize = 22; - const PPN_OFFSET: usize = 10; -} - #[cfg(feature = "riscv.pagetable.sv39")] impl PhysAddrPaging for PhysAddr { const PG_OFFSET: usize = 12; @@ -72,12 +65,6 @@ pub trait VirtAddrPaging { } } -#[cfg(feature = "riscv.pagetable.sv32")] -impl VirtAddrPaging for VirtAddr { - const PG_OFFSET: usize = 12; - const VPN_BITS: usize = 10; -} - #[cfg(feature = "riscv.pagetable.sv39")] impl VirtAddrPaging for VirtAddr { const PG_OFFSET: usize = 12; @@ -98,14 +85,9 @@ impl TableLevelSize for TableLevel { fn level_size(&self) -> usize { match self { Self::Level0 => 4 * KIB, - #[cfg(feature = "riscv.pagetable.sv32")] - Self::Level1 => 4 * MIB, - #[cfg(not(feature = "riscv.pagetable.sv32"))] Self::Level1 => 2 * MIB, Self::Level2 => 1 * GIB, - #[cfg(not(feature = "legacy"))] Self::Level3 => 512 * GIB, - #[cfg(not(feature = "legacy"))] Self::Level4 => 256 * TIB, } } diff --git a/lib/vspace/src/paging/table.rs b/lib/vspace/src/paging/table.rs index c1076a7..45079f9 100644 --- a/lib/vspace/src/paging/table.rs +++ b/lib/vspace/src/paging/table.rs @@ -7,9 +7,7 @@ pub enum TableLevel { Level0 = 0, // KiloPage Level1 = 1, // MegaPage Level2 = 2, // GigaPage - #[cfg(not(feature = "legacy"))] Level3 = 3, // TeraPage - #[cfg(not(feature = "legacy"))] Level4 = 4, // PetaPage } @@ -19,9 +17,7 @@ impl TableLevel { Self::Level0 => None, Self::Level1 => Some(Self::Level0), Self::Level2 => Some(Self::Level1), - #[cfg(not(feature = "legacy"))] Self::Level3 => Some(Self::Level2), - #[cfg(not(feature = "legacy"))] Self::Level4 => Some(Self::Level3), } } @@ -31,9 +27,7 @@ impl TableLevel { Self::Level0 => Some(Self::Level1), Self::Level1 => Some(Self::Level2), Self::Level2 => Some(Self::Level3), - #[cfg(not(feature = "legacy"))] Self::Level3 => Some(Self::Level4), - #[cfg(not(feature = "legacy"))] Self::Level4 => None, } } diff --git a/xtask/src/artifact.rs b/xtask/src/artifact.rs index 8ab2e12..2d3ab91 100644 --- a/xtask/src/artifact.rs +++ b/xtask/src/artifact.rs @@ -11,7 +11,6 @@ pub enum Profile { #[derive(ValueEnum, Copy, Clone)] #[value(rename_all = "snake_case")] pub enum Arch { - RISCV32, RISCV64, } @@ -32,8 +31,8 @@ impl Arch { pub fn rust_flags(&self) -> Vec { let mut flags = Self::FLAGS_RELOCATION.iter().map(|s| s.to_string()).collect::>(); match self { - Arch::RISCV32 | Arch::RISCV64 => { - flags.push(format!("-Clink-arg=-Tkernel/src/arch/riscv/linker{}.ld", self.bits())); + Arch::RISCV64 => { + flags.push("-Clink-arg=-Tkernel/src/arch/riscv/linker64.ld".to_string()); flags }, } @@ -41,13 +40,12 @@ impl Arch { pub fn triple(&self) -> String { match self { - Arch::RISCV32 | Arch::RISCV64 => format!("riscv{}imac-unknown-none-elf", self.bits()), + Arch::RISCV64 => "riscv64imac-unknown-none-elf".to_string(), } } pub fn bits(&self) -> u32 { match self { - Arch::RISCV32 => 32, Arch::RISCV64 => 64, } }