204 lines
5.4 KiB
Verilog
204 lines
5.4 KiB
Verilog
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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//--------------------------------------------------------------------------------
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//Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
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//Date : Mon Aug 8 22:48:00 2022
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//Host : Laptop-Paul running 64-bit Manjaro Linux
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//Command : generate_target mycpu_block_wrapper.bd
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//Design : mycpu_block_wrapper
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//Purpose : IP block netlist
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//--------------------------------------------------------------------------------
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`timescale 1 ps / 1 ps
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module mycpu_block_wrapper
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(clk,
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ddr3_addr,
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ddr3_ba,
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ddr3_cas_n,
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ddr3_ck_n,
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ddr3_ck_p,
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ddr3_cke,
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ddr3_dm,
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ddr3_dq,
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ddr3_dqs_n,
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ddr3_dqs_p,
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ddr3_odt,
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ddr3_ras_n,
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ddr3_reset_n,
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ddr3_we_n,
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mdio_rtl_0_mdc,
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mdio_rtl_0_mdio_io,
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mii_rtl_0_col,
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mii_rtl_0_crs,
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mii_rtl_0_rst_n,
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mii_rtl_0_rx_clk,
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mii_rtl_0_rx_dv,
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mii_rtl_0_rx_er,
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mii_rtl_0_rxd,
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mii_rtl_0_tx_clk,
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mii_rtl_0_tx_en,
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mii_rtl_0_txd,
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resetn_rtl_0,
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spi_rtl_0_io0_io,
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spi_rtl_0_io1_io,
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spi_rtl_0_sck_io,
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spi_rtl_0_ss_io,
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uart_rtl_0_cts,
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uart_rtl_0_dcd,
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uart_rtl_0_dsr,
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uart_rtl_0_dtr,
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uart_rtl_0_ri,
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uart_rtl_0_rts,
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uart_rtl_0_rxd,
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uart_rtl_0_txd);
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input clk;
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output [12:0]ddr3_addr;
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output [2:0]ddr3_ba;
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output ddr3_cas_n;
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output [0:0]ddr3_ck_n;
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output [0:0]ddr3_ck_p;
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output [0:0]ddr3_cke;
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output [1:0]ddr3_dm;
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inout [15:0]ddr3_dq;
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inout [1:0]ddr3_dqs_n;
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inout [1:0]ddr3_dqs_p;
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output [0:0]ddr3_odt;
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output ddr3_ras_n;
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output ddr3_reset_n;
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output ddr3_we_n;
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output mdio_rtl_0_mdc;
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inout mdio_rtl_0_mdio_io;
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input mii_rtl_0_col;
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input mii_rtl_0_crs;
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output mii_rtl_0_rst_n;
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input mii_rtl_0_rx_clk;
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input mii_rtl_0_rx_dv;
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input mii_rtl_0_rx_er;
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input [3:0]mii_rtl_0_rxd;
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input mii_rtl_0_tx_clk;
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output mii_rtl_0_tx_en;
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output [3:0]mii_rtl_0_txd;
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input resetn_rtl_0;
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inout spi_rtl_0_io0_io;
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inout spi_rtl_0_io1_io;
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output spi_rtl_0_sck_io;
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output [0:0] spi_rtl_0_ss_io;
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input uart_rtl_0_cts;
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input uart_rtl_0_dcd;
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input uart_rtl_0_dsr;
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output uart_rtl_0_dtr;
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input uart_rtl_0_ri;
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output uart_rtl_0_rts;
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input uart_rtl_0_rxd;
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output uart_rtl_0_txd;
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wire clk;
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wire [12:0]ddr3_addr;
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wire [2:0]ddr3_ba;
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wire ddr3_cas_n;
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wire [0:0]ddr3_ck_n;
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wire [0:0]ddr3_ck_p;
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wire [0:0]ddr3_cke;
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wire [1:0]ddr3_dm;
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wire [15:0]ddr3_dq;
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wire [1:0]ddr3_dqs_n;
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wire [1:0]ddr3_dqs_p;
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wire [0:0]ddr3_odt;
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wire ddr3_ras_n;
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wire ddr3_reset_n;
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wire ddr3_we_n;
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wire mdio_rtl_0_mdc;
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wire mdio_rtl_0_mdio_i;
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wire mdio_rtl_0_mdio_io;
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wire mdio_rtl_0_mdio_o;
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wire mdio_rtl_0_mdio_t;
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wire mii_rtl_0_col;
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wire mii_rtl_0_crs;
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wire mii_rtl_0_rst_n;
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wire mii_rtl_0_rx_clk;
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wire mii_rtl_0_rx_dv;
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wire mii_rtl_0_rx_er;
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wire [3:0]mii_rtl_0_rxd;
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wire mii_rtl_0_tx_clk;
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wire mii_rtl_0_tx_en;
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wire [3:0]mii_rtl_0_txd;
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wire resetn_rtl_0;
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wire spi_rtl_0_io0_io;
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wire spi_rtl_0_io1_io;
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wire spi_rtl_0_sck_io;
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wire [0:0]spi_rtl_0_ss_io;
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wire uart_rtl_0_cts;
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wire uart_rtl_0_dcd;
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wire uart_rtl_0_dsr;
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wire uart_rtl_0_dtr;
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wire uart_rtl_0_ri;
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wire uart_rtl_0_rts;
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wire uart_rtl_0_rxd;
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wire uart_rtl_0_txd;
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wire sdi_en_0, sdo_en_0;
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wire sdi_i_0, sdi_o_0;
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wire sdo_i_0, sdo_o_0;
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wire [3:0] csn_en_0;
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wire [3:0] csn_o_0;
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assign spi_rtl_0_ss_io[0] = ~csn_en_0[0] & csn_o_0[0];
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assign spi_rtl_0_io0_io = sdo_en_0 ? 1'bz : sdo_o_0 ;
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assign spi_rtl_0_io1_io = sdi_en_0 ? 1'bz : sdi_o_0 ;
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assign sdo_i_0 = spi_rtl_0_io0_io;
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assign sdi_i_0 = spi_rtl_0_io1_io;
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IOBUF mdio_rtl_0_mdio_iobuf
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(.I(mdio_rtl_0_mdio_o),
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.IO(mdio_rtl_0_mdio_io),
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.O(mdio_rtl_0_mdio_i),
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.T(mdio_rtl_0_mdio_t));
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mycpu_block mycpu_block_i
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(.clk(clk),
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.csn_en_0(csn_en_0),
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.csn_o_0(csn_o_0),
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.ddr3_addr(ddr3_addr),
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.ddr3_ba(ddr3_ba),
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.ddr3_cas_n(ddr3_cas_n),
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.ddr3_ck_n(ddr3_ck_n),
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.ddr3_ck_p(ddr3_ck_p),
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.ddr3_cke(ddr3_cke),
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.ddr3_dm(ddr3_dm),
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.ddr3_dq(ddr3_dq),
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.ddr3_dqs_n(ddr3_dqs_n),
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.ddr3_dqs_p(ddr3_dqs_p),
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.ddr3_odt(ddr3_odt),
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.ddr3_ras_n(ddr3_ras_n),
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.ddr3_reset_n(ddr3_reset_n),
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.ddr3_we_n(ddr3_we_n),
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.mdio_rtl_0_mdc(mdio_rtl_0_mdc),
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.mdio_rtl_0_mdio_i(mdio_rtl_0_mdio_i),
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.mdio_rtl_0_mdio_o(mdio_rtl_0_mdio_o),
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.mdio_rtl_0_mdio_t(mdio_rtl_0_mdio_t),
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.mii_rtl_0_col(mii_rtl_0_col),
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.mii_rtl_0_crs(mii_rtl_0_crs),
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.mii_rtl_0_rst_n(mii_rtl_0_rst_n),
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.mii_rtl_0_rx_clk(mii_rtl_0_rx_clk),
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.mii_rtl_0_rx_dv(mii_rtl_0_rx_dv),
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.mii_rtl_0_rx_er(mii_rtl_0_rx_er),
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.mii_rtl_0_rxd(mii_rtl_0_rxd),
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.mii_rtl_0_tx_clk(mii_rtl_0_tx_clk),
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.mii_rtl_0_tx_en(mii_rtl_0_tx_en),
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.mii_rtl_0_txd(mii_rtl_0_txd),
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.resetn_rtl_0(resetn_rtl_0),
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.sck_o_0(spi_rtl_0_sck_io),
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.sdi_en_0(sdi_en_0),
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.sdi_i_0(sdi_i_0),
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.sdi_o_0(sdi_o_0),
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.sdo_en_0(sdo_en_0),
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.sdo_i_0(sdo_i_0),
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.sdo_o_0(sdo_o_0),
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.uart_rtl_0_ctsn(~uart_rtl_0_cts),
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.uart_rtl_0_dcdn(~uart_rtl_0_dcd),
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.uart_rtl_0_dsrn(~uart_rtl_0_dsr),
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.uart_rtl_0_dtrn(~uart_rtl_0_dtr),
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.uart_rtl_0_ri(uart_rtl_0_ri),
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.uart_rtl_0_rtsn(~uart_rtl_0_rts),
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.uart_rtl_0_rxd(uart_rtl_0_rxd),
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.uart_rtl_0_txd(uart_rtl_0_txd));
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endmodule
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