//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. //-------------------------------------------------------------------------------- //Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022 //Date : Mon Aug 8 22:48:00 2022 //Host : Laptop-Paul running 64-bit Manjaro Linux //Command : generate_target mycpu_block_wrapper.bd //Design : mycpu_block_wrapper //Purpose : IP block netlist //-------------------------------------------------------------------------------- `timescale 1 ps / 1 ps module mycpu_block_wrapper (clk, ddr3_addr, ddr3_ba, ddr3_cas_n, ddr3_ck_n, ddr3_ck_p, ddr3_cke, ddr3_dm, ddr3_dq, ddr3_dqs_n, ddr3_dqs_p, ddr3_odt, ddr3_ras_n, ddr3_reset_n, ddr3_we_n, mdio_rtl_0_mdc, mdio_rtl_0_mdio_io, mii_rtl_0_col, mii_rtl_0_crs, mii_rtl_0_rst_n, mii_rtl_0_rx_clk, mii_rtl_0_rx_dv, mii_rtl_0_rx_er, mii_rtl_0_rxd, mii_rtl_0_tx_clk, mii_rtl_0_tx_en, mii_rtl_0_txd, resetn_rtl_0, spi_rtl_0_io0_io, spi_rtl_0_io1_io, spi_rtl_0_sck_io, spi_rtl_0_ss_io, uart_rtl_0_cts, uart_rtl_0_dcd, uart_rtl_0_dsr, uart_rtl_0_dtr, uart_rtl_0_ri, uart_rtl_0_rts, uart_rtl_0_rxd, uart_rtl_0_txd); input clk; output [12:0]ddr3_addr; output [2:0]ddr3_ba; output ddr3_cas_n; output [0:0]ddr3_ck_n; output [0:0]ddr3_ck_p; output [0:0]ddr3_cke; output [1:0]ddr3_dm; inout [15:0]ddr3_dq; inout [1:0]ddr3_dqs_n; inout [1:0]ddr3_dqs_p; output [0:0]ddr3_odt; output ddr3_ras_n; output ddr3_reset_n; output ddr3_we_n; output mdio_rtl_0_mdc; inout mdio_rtl_0_mdio_io; input mii_rtl_0_col; input mii_rtl_0_crs; output mii_rtl_0_rst_n; input mii_rtl_0_rx_clk; input mii_rtl_0_rx_dv; input mii_rtl_0_rx_er; input [3:0]mii_rtl_0_rxd; input mii_rtl_0_tx_clk; output mii_rtl_0_tx_en; output [3:0]mii_rtl_0_txd; input resetn_rtl_0; inout spi_rtl_0_io0_io; inout spi_rtl_0_io1_io; output spi_rtl_0_sck_io; output [0:0] spi_rtl_0_ss_io; input uart_rtl_0_cts; input uart_rtl_0_dcd; input uart_rtl_0_dsr; output uart_rtl_0_dtr; input uart_rtl_0_ri; output uart_rtl_0_rts; input uart_rtl_0_rxd; output uart_rtl_0_txd; wire clk; wire [12:0]ddr3_addr; wire [2:0]ddr3_ba; wire ddr3_cas_n; wire [0:0]ddr3_ck_n; wire [0:0]ddr3_ck_p; wire [0:0]ddr3_cke; wire [1:0]ddr3_dm; wire [15:0]ddr3_dq; wire [1:0]ddr3_dqs_n; wire [1:0]ddr3_dqs_p; wire [0:0]ddr3_odt; wire ddr3_ras_n; wire ddr3_reset_n; wire ddr3_we_n; wire mdio_rtl_0_mdc; wire mdio_rtl_0_mdio_i; wire mdio_rtl_0_mdio_io; wire mdio_rtl_0_mdio_o; wire mdio_rtl_0_mdio_t; wire mii_rtl_0_col; wire mii_rtl_0_crs; wire mii_rtl_0_rst_n; wire mii_rtl_0_rx_clk; wire mii_rtl_0_rx_dv; wire mii_rtl_0_rx_er; wire [3:0]mii_rtl_0_rxd; wire mii_rtl_0_tx_clk; wire mii_rtl_0_tx_en; wire [3:0]mii_rtl_0_txd; wire resetn_rtl_0; wire spi_rtl_0_io0_io; wire spi_rtl_0_io1_io; wire spi_rtl_0_sck_io; wire [0:0]spi_rtl_0_ss_io; wire uart_rtl_0_cts; wire uart_rtl_0_dcd; wire uart_rtl_0_dsr; wire uart_rtl_0_dtr; wire uart_rtl_0_ri; wire uart_rtl_0_rts; wire uart_rtl_0_rxd; wire uart_rtl_0_txd; wire sdi_en_0, sdo_en_0; wire sdi_i_0, sdi_o_0; wire sdo_i_0, sdo_o_0; wire [3:0] csn_en_0; wire [3:0] csn_o_0; assign spi_rtl_0_ss_io[0] = ~csn_en_0[0] & csn_o_0[0]; assign spi_rtl_0_io0_io = sdo_en_0 ? 1'bz : sdo_o_0 ; assign spi_rtl_0_io1_io = sdi_en_0 ? 1'bz : sdi_o_0 ; assign sdo_i_0 = spi_rtl_0_io0_io; assign sdi_i_0 = spi_rtl_0_io1_io; IOBUF mdio_rtl_0_mdio_iobuf (.I(mdio_rtl_0_mdio_o), .IO(mdio_rtl_0_mdio_io), .O(mdio_rtl_0_mdio_i), .T(mdio_rtl_0_mdio_t)); mycpu_block mycpu_block_i (.clk(clk), .csn_en_0(csn_en_0), .csn_o_0(csn_o_0), .ddr3_addr(ddr3_addr), .ddr3_ba(ddr3_ba), .ddr3_cas_n(ddr3_cas_n), .ddr3_ck_n(ddr3_ck_n), .ddr3_ck_p(ddr3_ck_p), .ddr3_cke(ddr3_cke), .ddr3_dm(ddr3_dm), .ddr3_dq(ddr3_dq), .ddr3_dqs_n(ddr3_dqs_n), .ddr3_dqs_p(ddr3_dqs_p), .ddr3_odt(ddr3_odt), .ddr3_ras_n(ddr3_ras_n), .ddr3_reset_n(ddr3_reset_n), .ddr3_we_n(ddr3_we_n), .mdio_rtl_0_mdc(mdio_rtl_0_mdc), .mdio_rtl_0_mdio_i(mdio_rtl_0_mdio_i), .mdio_rtl_0_mdio_o(mdio_rtl_0_mdio_o), .mdio_rtl_0_mdio_t(mdio_rtl_0_mdio_t), .mii_rtl_0_col(mii_rtl_0_col), .mii_rtl_0_crs(mii_rtl_0_crs), .mii_rtl_0_rst_n(mii_rtl_0_rst_n), .mii_rtl_0_rx_clk(mii_rtl_0_rx_clk), .mii_rtl_0_rx_dv(mii_rtl_0_rx_dv), .mii_rtl_0_rx_er(mii_rtl_0_rx_er), .mii_rtl_0_rxd(mii_rtl_0_rxd), .mii_rtl_0_tx_clk(mii_rtl_0_tx_clk), .mii_rtl_0_tx_en(mii_rtl_0_tx_en), .mii_rtl_0_txd(mii_rtl_0_txd), .resetn_rtl_0(resetn_rtl_0), .sck_o_0(spi_rtl_0_sck_io), .sdi_en_0(sdi_en_0), .sdi_i_0(sdi_i_0), .sdi_o_0(sdi_o_0), .sdo_en_0(sdo_en_0), .sdo_i_0(sdo_i_0), .sdo_o_0(sdo_o_0), .uart_rtl_0_ctsn(~uart_rtl_0_cts), .uart_rtl_0_dcdn(~uart_rtl_0_dcd), .uart_rtl_0_dsrn(~uart_rtl_0_dsr), .uart_rtl_0_dtrn(~uart_rtl_0_dtr), .uart_rtl_0_ri(uart_rtl_0_ri), .uart_rtl_0_rtsn(~uart_rtl_0_rts), .uart_rtl_0_rxd(uart_rtl_0_rxd), .uart_rtl_0_txd(uart_rtl_0_txd)); endmodule