117 lines
8.6 KiB
Markdown
117 lines
8.6 KiB
Markdown
Magically Improved Pipeline Stages
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===
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Our awesome `MIPS` CPU written in `SystemVerilog` for Loongson Cup
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```
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.
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├── resources <-- 资源包
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├── src <-- CPU设计代码
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│ ├── AXI <-- AXI总线交互
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│ ├── Cache <-- Cache
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│ ├── Core <-- CPU核心
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│ ├── CP0 <-- CP0协处理器
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│ ├── include <-- 头文件
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│ ├── IP <-- 用到的IP
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│ └── MMU <-- 地址转换单元
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└── tools <-- 控制信号生成器
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```
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## Progress
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- [x] 特权模式
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- [x] `CP0`寄存器`Status.UM` :heavy_check_mark:
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- [x] 访存异常(考虑`in_kernel`状态切换带来的冒险) :heavy_check_mark:
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- [x] 特权指令异常 :heavy_check_mark:
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- [ ] 浮点运算单元
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- [ ] ~~做一个真的`FPU`~~ :x:
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- [ ] 浮点运算指令报`Coprocessor Unusable`，同时`CP0`中新增`Cause.CE` :clock3:
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- [ ] 新增指令
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| Status | Instruction | Type | Tier | Comment |
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| :----------------: | :-------------------------------: | :------: | :--: | :-------------------------------------- |
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| :heavy_check_mark: | `I-Cache Index Invalid` | `SYS` | 2 | |
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| :heavy_check_mark: | `I-Cache Hit Invalid` | `SYS` | 2 | |
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| :heavy_check_mark: | `D-Cache Index Writeback Invalid` | `SYS` | 2 | :cry: |
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| :heavy_check_mark: | `D-Cache Index Store Tag` | `SYS` | 2 | |
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| :heavy_check_mark: | `D-Cache Hit Invalid` | `SYS` | 2 | |
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| :heavy_check_mark: | `D-Cache Hit Writeback Invalid` | `SYS` | 2 | |
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| :heavy_check_mark: | `PREF` | `SYS` | 1 | Treat as `NOP` |
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| :heavy_check_mark: | `SYNC` | `SYS` | 1 | Treat as `NOP` (We're strongly ordered) |
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| :clock3: | `WAIT` | `SYS` | 2 | |
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| :heavy_check_mark: | `TEQ` | `SYS` | 2 | |
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| :heavy_check_mark: | `TEQI` | `SYS` | 2 | |
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| :heavy_check_mark: | `TGE` | `SYS` | 2 | |
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| :heavy_check_mark: | `TGEI` | `SYS` | 2 | |
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| :heavy_check_mark: | `TGEIU` | `SYS` | 2 | |
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| :heavy_check_mark: | `TGEU` | `SYS` | 2 | |
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| :heavy_check_mark: | `TLT` | `SYS` | 2 | |
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| :heavy_check_mark: | `TLTI` | `SYS` | 2 | |
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| :heavy_check_mark: | `TLTIU` | `SYS` | 2 | |
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| :heavy_check_mark: | `TLTU` | `SYS` | 2 | |
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| :heavy_check_mark: | `TNE` | `SYS` | 2 | |
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| :heavy_check_mark: | `TNEI` | `SYS` | 2 | |
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| :clock3: | `CLO` | `ARITH` | 2 | `RT == RD` |
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| :clock3: | `CLZ` | `ARITH` | 2 | `RT == RD` |
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| :heavy_check_mark: | `MADD` | `ARITH` | 2 | `M`阶段加一个流水级 |
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| :heavy_check_mark: | `MADDU` | `ARITH` | 2 | `M`阶段加一个流水级 |
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| :heavy_check_mark: | `MSUB` | `ARITH` | 2 | `M`阶段加一个流水级 |
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| :heavy_check_mark: | `MSUBU` | `ARITH` | 2 | `M`阶段加一个流水级 |
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| :heavy_check_mark: | `MOVN` | `ARITH` | 2 | |
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| :heavy_check_mark: | `MOVZ` | `ARITH` | 2 | |
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| :x: | `LL` | `MEM` | 3 | 修改内核去除相关指令 |
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| :heavy_check_mark: | `LWL` | `MEM` | 1 | |
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| :heavy_check_mark: | `LWR` | `MEM` | 1 | |
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| :x: | `SC` | `MEM` | 3 | 修改内核去除相关指令 |
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| :heavy_check_mark: | `SWL` | `MEM` | 1 | |
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| :heavy_check_mark: | `SWR` | `MEM` | 1 | |
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| :x: | `BEQL` | `BRANCH` | 3 | 修改编译指令 |
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| :x: | `BGEZALL` | `BRANCH` | 3 | 修改编译指令 |
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| :x: | `BGEZL` | `BRANCH` | 3 | 修改编译指令 |
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| :x: | `BGTZL` | `BRANCH` | 3 | 修改编译指令 |
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| :x: | `BLEZL` | `BRANCH` | 3 | 修改编译指令 |
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| :x: | `BLTZALL` | `BRANCH` | 3 | 修改编译指令 |
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| :x: | `BLTZL` | `BRANCH` | 3 | 修改编译指令 |
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| :x: | `BNEL` | `BRANCH` | 3 | 修改编译指令 |
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## `Cache`指令
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预计实现以下`7`条操作
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```verilog
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32'b101111?????00000???????????????? // I-Cache Index Invalid
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32'b101111?????01000???????????????? // I-Cache Index Store Tag
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32'b101111?????10000???????????????? // I-Cache Hit Invalid
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32'b101111?????00001???????????????? // D-Cache Index Writeback Invalid
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32'b101111?????01001???????????????? // D-Cache Index Store Tag
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32'b101111?????10001???????????????? // D-Cache Hit Invalid
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32'b101111?????10101???????????????? // D-Cache Hit Writeback Invalid
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```
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其中，`Index Store Tag`中使用到了`TagLo`和`TagHi`寄存器。考虑到地址最多`32`位，故不实现`TagHi`寄存器(恒`0`)；同时，由于`TagLo`和`TagHi`寄存器定义与具体处理器实现相关，在应用上用于将`Cache`的`Tag`清零（可以魔改内核），故也不实现`TagLo`寄存器(恒`0`)。所以`Index Store Tag`指令在实现上变为不写回的`Index Invalid`
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对于上述操作，具体实现：
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```
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Cache -> VIPT
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Index Invalid : VA -> Index -> (Write Back) -> Write Zero
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Index Store Tag : VA -> Index -> Write Zero
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Hit Invalid : VA -> Lookup -> Hit? -> Write Zero
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Hit Writeback Invalid : VA -> Lookup -> Hit? -> (Write Back) -> Write Zero
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```
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控制信号：
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| `CacheOp[2]` | `CacheOp[1]` | `CacheOp[0]` | Name |
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| :------------------------: | :---------------------: | :----------------------------: | :---: |
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| 0 | 0 | 0 | `NOP` |
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| 0 | 0 | 1 | |
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| 0 | 1 | ? | |
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| 1 | 0 | 0 | |
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| 1 | 0 | 1 | |
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| 1 | 1 | 0 | |
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| 1 | 1 | 1 | |
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| `I-Cache(0) or D-Cache(1)` | `Lookup(0) or Index(1)` | `WriteBack(0) or WriteOnly(1)` | |
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`Todo`: 涉及`I-Cache`的`CACHE`指令需要清空流水线
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