Paul Pan 7b33e4213a a big update ... 1. add test soft 2. modify verilator (TODO: crossbar need to replace) 3. fix CP0: now CU0 is always 1 4. Controller: cacheop 5. Controller: fix TEN 6. mycpu_top fix CP0_i 7. fix AXI.sv 8. fix AXIReader.sv 9. fix AXIWriter.sv: getting the correct data and length 10. MU: fix cache writeback, fix mem data mux, fix writer address, fix read request		2022-07-29 18:25:58 +08:00
..
arbiter.v	feat: MU rewrite 1	2022-07-27 15:07:16 +08:00
axi_crossbar_addr.v	feat: MU rewrite 1	2022-07-27 15:07:16 +08:00
axi_crossbar_rd.v	feat: MU rewrite 1	2022-07-27 15:07:16 +08:00
axi_crossbar_wr.v	feat: MU rewrite 1	2022-07-27 15:07:16 +08:00
axi_crossbar.v	a big update	2022-07-29 18:25:58 +08:00
axi_ram.v	a big update	2022-07-29 18:25:58 +08:00
axi_register_rd.v	feat: MU rewrite 1	2022-07-27 15:07:16 +08:00
axi_register_wr.v	feat: MU rewrite 1	2022-07-27 15:07:16 +08:00
div_signed.sv	feat: MU rewrite 1	2022-07-27 15:07:16 +08:00
div_unsigned.sv	feat: MU rewrite 1	2022-07-27 15:07:16 +08:00
mul_signed.sv	feat: MU rewrite 1	2022-07-27 15:07:16 +08:00
mul_unsigned.sv	feat: MU rewrite 1	2022-07-27 15:07:16 +08:00
priority_encoder.v	feat: MU rewrite 1	2022-07-27 15:07:16 +08:00