Paul Pan
7b33e4213a
1. add test soft 2. modify verilator (TODO: crossbar need to replace) 3. fix CP0: now CU0 is always 1 4. Controller: cacheop 5. Controller: fix TEN 6. mycpu_top fix CP0_i 7. fix AXI.sv 8. fix AXIReader.sv 9. fix AXIWriter.sv: getting the correct data and length 10. MU: fix cache writeback, fix mem data mux, fix writer address, fix read request
357 lines
6.0 KiB
ArmAsm
357 lines
6.0 KiB
ArmAsm
#include <asm.h>
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#include <regdef.h>
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#include <ucas_cde.h>
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#define TEST_TLB_EXCEPTION 1
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#if TEST_TLB_EXCEPTION
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#define TEST_NUM 10
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#else
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#define TEST_NUM 7
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#endif
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##s0, number
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##s1, number adress
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##s2, exception use
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##s3, score
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##s4, exception pc
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.set noreorder
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.globl _start
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.globl start
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.globl __main
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_start:
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start:
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disable_trace_cmp_s
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j locate
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nop
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##avoid "j locate" not taken
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lui t0, 0x8000
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addiu t1, t1, 1
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or t2, t0, zero
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addu t3, t5, t6
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lw t4, 0(t0)
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nop
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##avoid cpu run error
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.org 0x0e8
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lui t0, 0x8000
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addiu t1, t1, 1
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or t2, t0, zero
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addu t3, t5, t6
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lw t4, 0(t0)
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nop
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.org 0x100
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test_finish:
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addiu t0, t0, 1
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b test_finish
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nop
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##avoid cpu run error
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lui t0, 0x8000
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addiu t1, t1, 1
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or t2, t0, zero
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addu t3, t5, t6
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lw t4, 0(t0)
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/*
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* exception handle
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*/
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.org 0x200
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tlb_refill:
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mfc0 k0, c0_cause
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andi k0, k0, 0x7c # 6..2
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li k1, 1
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beq s2, k1, load_refill_ex
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nop
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li k1, 2
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beq s2, k1, store_refill_ex
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nop
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li k1, 3
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beq s2, k1, fetch_refill_ex
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nop
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b tlb_fail
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nop
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load_refill_ex:
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li k1, 2<<2 # exception: tlbl
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bne k0, k1, tlb_fail
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nop
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mfc0 k0, c0_epc
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la k1, load_tlb_pc_1
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bne k0, k1, tlb_fail
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nop
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li t1, 0x00234500
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mtc0 t1, c0_entrylo0
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li t2, 0x00789a00
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mtc0 t2, c0_entrylo1
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li t3, 0x1
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mtc0 t3, c0_index
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tlbwi
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nop
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.set mips32
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eret
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.set mips0
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store_refill_ex:
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li k1, 3<<2 # exception: tlbs
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bne k0, k1, tlb_fail
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nop
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mfc0 k0, c0_epc
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la k1, store_tlb_pc_1
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bne k0, k1, tlb_fail
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nop
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li t1, 0x00234500
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mtc0 t1, c0_entrylo0
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li t2, 0x00789a00
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mtc0 t2, c0_entrylo1
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li t3, 0x2
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mtc0 t3, c0_index
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tlbwi
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nop
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.set mips32
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eret
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.set mips0
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fetch_refill_ex:
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li k1, 2<<2 # exception: tlbl
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bne k0, k1, tlb_fail
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nop
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la k1,fetch_tlb_pc_2
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andi k1, k1, 0xfff
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li k0, 0x33333000
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or k1, k1, k0
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mfc0 k0, c0_epc
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bne k0, k1, tlb_fail
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nop
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li t1, 0x00234500
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mtc0 t1, c0_entrylo0
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li t2, 0x00789a00
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mtc0 t2, c0_entrylo1
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li t3, 0x3
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mtc0 t3, c0_index
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tlbwi
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nop
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.set mips32
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eret
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.set mips0
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.org 0x380
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1:
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mfc0 k0, c0_cause
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andi k0, k0, 0x7c # 6..2
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li k1, 1
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beq s2, k1, load_inv_ex
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nop
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li k1, 2
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beq s2, k1, store_inv_mod_ex
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nop
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li k1, 3
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beq s2, k1, fetch_inv_ex
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nop
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b tlb_fail
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nop
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load_inv_ex:
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li k1, 2<<2 # exception: tlbl
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beq k0, k1, load_tlb_invalid
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nop
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b tlb_fail
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nop
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load_tlb_invalid:
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tlbp
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mfc0 k0, c0_epc
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la k1, load_tlb_pc_1
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bne k0, k1, tlb_fail
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nop
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addiu k0, k0, 8
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mtc0 k0, c0_epc
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li k0, (0xbfcdf<<6)|2 #valid
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mtc0 k0, c0_entrylo0
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li k1, (0xbfcd0<<6)|2 #valid
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mtc0 k1, c0_entrylo1
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tlbwi
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li s2, 0x1111
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.set mips32
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eret
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.set mips0
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store_inv_mod_ex:
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li k1, 3<<2 # exception: tlbs
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beq k0, k1, store_tlb_invalid
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nop
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li k1, 1<<2 # exception: mod
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beq k0, k1, store_tlb_modified
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nop
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b tlb_fail
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nop
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store_tlb_invalid:
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tlbp
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mfc0 k0, c0_epc
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la k1, store_tlb_pc_1
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bne k0, k1, tlb_fail
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nop
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li k0, (0xbfcd1<<6)|2 #valid
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mtc0 k0, c0_entrylo0
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li k1, (0xbfc20<<6)|2 #valid
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mtc0 k1, c0_entrylo1
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tlbwi
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.set mips32
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eret
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.set mips0
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store_tlb_modified:
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mfc0 k0, c0_epc
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la k1, store_tlb_pc_1
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bne k0, k1, tlb_fail
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nop
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addiu k0, k0, 8
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mtc0 k0, c0_epc
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li k0, (0xbfcd1<<6)|6 #dirty,valid
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mtc0 k0, c0_entrylo0
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li k1, (0xbfc20<<6)|2 #valid
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mtc0 k1, c0_entrylo1
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tlbwi
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li s2, 0x2222
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.set mips32
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eret
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.set mips0
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fetch_inv_ex:
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li k1, 2<<2 # exception: tlbl
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beq k0, k1, fetch_tlb_invalid
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nop
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b tlb_fail
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nop
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fetch_tlb_invalid:
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tlbp
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la k1,fetch_tlb_pc_2
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andi k1, k1, 0xfff
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li k0, 0x33333000
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or k1, k1, k0
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mfc0 k0, c0_epc
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bne k0, k1, tlb_fail
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nop
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li k0, (0xbfcdf<<6)|2 #valid
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mtc0 k0, c0_entrylo0
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la k1, fetch_tlb_pc_2
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srl k1, 12
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sll k1, 6
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ori k1, k1, 2 #valid
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mtc0 k1, c0_entrylo1
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tlbwi
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nop
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nop
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li s2, 0x3333
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.set mips32
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eret
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.set mips0
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tlb_fail:
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sll t1, s0, 24
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or t0, t1, s3
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sw t0, 0(s1)
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jr ra
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nop
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locate:
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.set noreorder
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LI (a0, LED_RG1_ADDR)
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LI (a1, LED_RG0_ADDR)
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LI (a2, LED_ADDR)
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LI (s1, NUM_ADDR)
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LI (t1, 0x0002)
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LI (t2, 0x0001)
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LI (t3, 0x0000ffff)
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lui s3, 0
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sw t1, 0(a0)
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sw t2, 0(a1)
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sw t3, 0(a2)
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sw s3, 0(s1)
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lui s0, 0
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inst_test:
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jal n1_index_test
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nop
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jal wait_1s
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nop
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jal n2_entryhi_test
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nop
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jal wait_1s
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nop
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jal n3_entrylo0_test
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nop
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jal wait_1s
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nop
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jal n4_entrylo1_test
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nop
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jal wait_1s
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nop
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jal n5_pagemask_test
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nop
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jal wait_1s
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nop
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jal n6_tlbwi_tlbr_test
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nop
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jal wait_1s
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nop
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jal n7_tlbp_test
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nop
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jal wait_1s
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nop
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#if TEST_TLB_EXCEPTION
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jal n8_load_tlb_ex_test
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nop
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jal wait_1s
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nop
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jal n9_store_tlb_ex_test
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nop
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jal wait_1s
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nop
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jal n10_fetch_tlb_ex_test
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nop
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jal wait_1s
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nop
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#endif
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test_end:
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LI (s0, TEST_NUM)
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beq s0, s3, 1f
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nop
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LI (a0, LED_ADDR)
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LI (a1, LED_RG1_ADDR)
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LI (a2, LED_RG0_ADDR)
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LI (t1, 0x0002)
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sw zero, 0(a0)
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sw t1, 0(a1)
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sw t1, 0(a2)
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b 2f
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nop
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1:
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LI (t1, 0x0001)
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LI (a0, LED_RG1_ADDR)
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LI (a1, LED_RG0_ADDR)
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sw t1, 0(a0)
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sw t1, 0(a1)
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2:
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j test_finish
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nop
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wait_1s:
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LI (t1,SIMU_FLAG_ADDR)
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lui t0, 0x0
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lw t2, 0x0(t1)
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bne t2, zero, 1f
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nop
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LI (t0,SWITCH_ADDR)
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lw t0, 0x0(t0) #switch[7:0]
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LI (t1, 0xff)
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xor t0, t0, t1
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sll t0, t0, 16 #t0 = switch<<16
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1:
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addiu t0, 1
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2:
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addiu t0, -1
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bne t0,zero, 2b
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nop
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jr ra
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nop
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