84 lines
5.1 KiB
Markdown
84 lines
5.1 KiB
Markdown
Magically Improved Pipeline Stages
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===
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Our awesome `MIPS` CPU written in `SystemVerilog` for Loongson Cup
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```
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.
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├── resources <-- 资源包
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│ └── 2021 <-- 2021年资源包
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│ ├── cpu132_gettrace <-- 性能测试基准(gs132)
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│ ├── soc_axi_func <-- AXI功能测试
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│ ├── soc_axi_perf <-- AXI性能测试
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│ ├── soc_axi_system <-- AXI系统测试
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│ └── soft <-- 测试用程序
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│ ├── func <-- 功能测试
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│ ├── memory_game <-- 记忆游戏
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│ └── perf_func <-- 性能测试
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├── src <-- CPU设计代码
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│ ├── AXI <-- AXI总线交互
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│ ├── Cache <-- Cache
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│ ├── Core <-- CPU核心
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│ ├── CP0 <-- CP0协处理器
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│ ├── include <-- 头文件
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│ ├── IP <-- 用到的IP
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│ ├── MMU <-- 地址转换单元
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│ └── testbench <-- 测试脚本
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└── tools <-- controller生成器
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```
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## TODO & Notice
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- [ ] 特权模式
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- [x] `CP0`寄存器`Status.UM` :heavy_check_mark:
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- [ ] 访存异常(考虑`in_kernel`状态切换带来的冒险) :hourglass:
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- [ ] 特权指令异常 :clock3:
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- [ ] 浮点运算单元
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- [ ] ~~做一个真的`FPU`~~ :x:
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- [ ] 浮点运算指令报`Coprocessor Unusable`，同时`CP0`中新增`Cause.CE` :clock3:
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- [ ] 新增指令
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| Status | Instruction | Type | Tier | Comment |
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| :------: | :---------: | :------: | :--: | :-------------------------------------- |
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| :clock3: | `Cache` | `SYS` | 3 | |
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| :clock3: | `PREF` | `SYS` | 1 | Treat as `NOP` |
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| :clock3: | `SYNC` | `SYS` | 1 | Treat as `NOP` (We're strongly ordered) |
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| :clock3: | `WAIT` | `SYS` | 3 | |
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| :clock3: | `TEQ` | `SYS` | 2 | |
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| :clock3: | `TEQI` | `SYS` | 2 | |
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| :clock3: | `TGE` | `SYS` | 2 | |
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| :clock3: | `TGEI` | `SYS` | 2 | |
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| :clock3: | `TGEIU` | `SYS` | 2 | |
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| :clock3: | `TGEU` | `SYS` | 2 | |
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| :clock3: | `TLT` | `SYS` | 2 | |
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| :clock3: | `TLTI` | `SYS` | 2 | |
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| :clock3: | `TLTIU` | `SYS` | 2 | |
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| :clock3: | `TLTU` | `SYS` | 2 | |
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| :clock3: | `TNE` | `SYS` | 2 | |
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| :clock3: | `TNEI` | `SYS` | 2 | |
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| :clock3: | `CLO` | `ARITH` | 2 | `RT == RD` |
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| :clock3: | `CLZ` | `ARITH` | 2 | `RT == RD` |
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| :clock3: | `MADD` | `ARITH` | 2 | |
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| :clock3: | `MADDU` | `ARITH` | 2 | |
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| :clock3: | `MSUB` | `ARITH` | 2 | |
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| :clock3: | `MSUBU` | `ARITH` | 2 | |
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| :clock3: | `MOVN` | `ARITH` | 1 | |
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| :clock3: | `MOVZ` | `ARITH` | 1 | |
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| :clock3: | `LL` | `MEM` | 3 | |
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| :clock3: | `LWL` | `MEM` | 1 | |
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| :clock3: | `LWR` | `MEM` | 1 | |
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| :clock3: | `SC` | `MEM` | 3 | |
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| :clock3: | `SWL` | `MEM` | 1 | |
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| :clock3: | `SWR` | `MEM` | 1 | |
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| :clock3: | `MOVF` | `FP` | 2 | |
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| :clock3: | `MOVT` | `FP` | 2 | |
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| :clock3: | `BEQL` | `BRANCH` | 3 | |
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| :clock3: | `BGEZALL` | `BRANCH` | 3 | |
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| :clock3: | `BGEZL` | `BRANCH` | 3 | |
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| :clock3: | `BGTZL` | `BRANCH` | 3 | |
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| :clock3: | `BLEZL` | `BRANCH` | 3 | |
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| :clock3: | `BLTZALL` | `BRANCH` | 3 | |
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| :clock3: | `BLTZL` | `BRANCH` | 3 | |
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| :clock3: | `BNEL` | `BRANCH` | 3 | |
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