Commit Graph

6 Commits

Author SHA1 Message Date
56cc2e5dcb fix: MU wstrb could directly passthrough 2022-07-29 23:25:14 +08:00
b25fbb5ee1 fix: multiply model 2022-07-29 18:48:58 +08:00
bf7ee46645 feat: reconfigure crossbar 2022-07-29 18:26:27 +08:00
7b33e4213a a big update
1. add test soft
2. modify verilator (TODO: crossbar need to replace)
3. fix CP0: now CU0 is always 1
4. Controller: cacheop
5. Controller: fix TEN
6. mycpu_top fix CP0_i
7. fix AXI.sv
8. fix AXIReader.sv
9. fix AXIWriter.sv: getting the correct data and length
10. MU: fix cache writeback, fix mem data mux, fix writer address, fix read request
2022-07-29 18:25:58 +08:00
4f7fe2adf2 feat: MU rewrite 2
TLB Support
2022-07-27 18:11:54 +08:00
9ce588757d feat: MU rewrite 1
1. ALU format
2. FIX hazard (MOVN / MOVZ)
3. verilator support
2022-07-27 15:07:16 +08:00