mmu write data_ok test
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cad94e7667
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f6270c5a65
@ -266,14 +266,17 @@ module MMU (
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case (drState)
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case (drState)
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DR_IDLE: begin
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DR_IDLE: begin
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if (~dValid1) dEn = 1;
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if (~dValid1) dEn = 1;
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else if (dwr1 & (~dCached1 | dc.hit)) drNextState = DR_REFILL;
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else begin
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else if (dCached1 & dc.hit) begin
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if (dwr1) data.data_ok = 1;
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dEn = 1;
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if (dwr1 & (~dCached1 | dc.hit)) drNextState = DR_REFILL;
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data.data_ok = 1;
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else if (dCached1 & dc.hit) begin
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end else begin
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dEn = 1;
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rdata_axi.req = 1;
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data.data_ok = 1;
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if (~rdata_axi.addr_ok) drNextState = DR_WA;
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end else begin
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else drNextState = DR_WD1;
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rdata_axi.req = 1;
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if (~rdata_axi.addr_ok) drNextState = DR_WA;
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else drNextState = DR_WD1;
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end
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end
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end
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end
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end
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DR_WA: begin
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DR_WA: begin
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@ -312,7 +315,6 @@ module MMU (
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DR_REFILL: begin
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DR_REFILL: begin
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if (wdata_ok) begin // TODO
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if (wdata_ok) begin // TODO
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dEn = 1;
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dEn = 1;
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if (dwr1) data.data_ok = 1;
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drNextState = DR_IDLE;
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drNextState = DR_IDLE;
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end
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end
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end
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end
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