From f6270c5a652073a65e9d9210c1fdcfe9ef6bced0 Mon Sep 17 00:00:00 2001
From: cxy004 <cxy004@qq.com>
Date: Sun, 1 Aug 2021 18:13:59 +0800
Subject: [PATCH] mmu write data_ok test

---
 src/MMU/MMU.sv | 20 +++++++++++---------
 1 file changed, 11 insertions(+), 9 deletions(-)

diff --git a/src/MMU/MMU.sv b/src/MMU/MMU.sv
index ae6aaaf..a892ce3 100644
--- a/src/MMU/MMU.sv
+++ b/src/MMU/MMU.sv
@@ -266,14 +266,17 @@ module MMU (
     case (drState)
       DR_IDLE: begin
         if (~dValid1) dEn = 1;
-        else if (dwr1 & (~dCached1 | dc.hit)) drNextState = DR_REFILL;
-        else if (dCached1 & dc.hit) begin
-          dEn = 1;
-          data.data_ok = 1;
-        end else begin
-          rdata_axi.req = 1;
-          if (~rdata_axi.addr_ok) drNextState = DR_WA;
-          else drNextState = DR_WD1;
+        else begin
+          if (dwr1) data.data_ok = 1;
+          if (dwr1 & (~dCached1 | dc.hit)) drNextState = DR_REFILL;
+          else if (dCached1 & dc.hit) begin
+            dEn = 1;
+            data.data_ok = 1;
+          end else begin
+            rdata_axi.req = 1;
+            if (~rdata_axi.addr_ok) drNextState = DR_WA;
+            else drNextState = DR_WD1;
+          end
         end
       end
       DR_WA: begin
@@ -312,7 +315,6 @@ module MMU (
       DR_REFILL: begin
         if (wdata_ok) begin  // TODO
           dEn = 1;
-          if (dwr1) data.data_ok = 1;
           drNextState = DR_IDLE;
         end
       end