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mmu write data_ok test

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cxy004 2021-08-01 18:13:59 +08:00
parent cad94e7667
commit f6270c5a65
1 changed files with 11 additions and 9 deletions
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6
src/MMU/MMU.sv
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@ -266,7 +266,9 @@ module MMU (
case (drState) case (drState)
DR_IDLE: begin DR_IDLE: begin
if (~dValid1) dEn = 1; if (~dValid1) dEn = 1;
else if (dwr1 & (~dCached1 | dc.hit)) drNextState = DR_REFILL; else begin
if (dwr1) data.data_ok = 1;
if (dwr1 & (~dCached1 | dc.hit)) drNextState = DR_REFILL;
else if (dCached1 & dc.hit) begin else if (dCached1 & dc.hit) begin
dEn = 1; dEn = 1;
data.data_ok = 1; data.data_ok = 1;
@ -276,6 +278,7 @@ module MMU (
else drNextState = DR_WD1; else drNextState = DR_WD1;
end end
end end
end
DR_WA: begin DR_WA: begin
rdata_axi.req = 1; rdata_axi.req = 1;
if (rdata_axi.addr_ok) begin if (rdata_axi.addr_ok) begin
@ -312,7 +315,6 @@ module MMU (
DR_REFILL: begin DR_REFILL: begin
if (wdata_ok) begin // TODO if (wdata_ok) begin // TODO
dEn = 1; dEn = 1;
if (dwr1) data.data_ok = 1;
drNextState = DR_IDLE; drNextState = DR_IDLE;
end end
end end