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fix4'

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This commit is contained in:
cxy004 2021-07-30 15:30:37 +08:00
parent 99436d9a42
commit f4fb6c49a1
2 changed files with 9 additions and 8 deletions
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6
src/Core/Datapath.sv
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@ -200,10 +200,10 @@ module Datapath (
prio_mux5 #(32) PF_pc_mux ( prio_mux5 #(32) PF_pc_mux (
PF_pc0, PF_pc0,
PF_pcp8, PF_pcp8,
C0_EPC,
`PCEXC, `PCEXC,
C0_EPC,
`PCRST, `PCRST,
{~F_valid, C0_exception.ExcValid, C0_exception.ERET, ~D_IA_valid}, {~F_valid, C0_exception.ExcValid, ~D_IA_valid},
PF.pc PF.pc
); );
@ -212,7 +212,7 @@ module Datapath (
assign PF_req = ~D.IA_ExcValid & ~D.IB_ExcValid & ~E.I0.ExcValid & ~E.I1.ExcValid; assign PF_req = ~D.IA_ExcValid & ~D.IB_ExcValid & ~E.I0.ExcValid & ~E.I1.ExcValid;
assign PF_go = PF.pc[1:0] == 2'b00 & PF_req; assign PF_go = PF.pc[1:0] == 2'b00 & PF_req;
assign fetch_i.req = rst | C0_exception.ExcValid | C0_exception.ERET | ~D_IA_valid assign fetch_i.req = rst | C0_exception.ERET | C0_exception.ExcValid | ~D_IA_valid
| PF_go & (~D.IA.PFCtrl.BJRJ | D_IA_can_dispatch) | PF_go & (~D.IA.PFCtrl.BJRJ | D_IA_can_dispatch)
& ( ~IQ_valids[3] & ( ~IQ_valids[3]
| ~IQ_valids[2] & (PF.pc[2] | F.pc[2] | D_readygo | D_readygo1) | ~IQ_valids[2] & (PF.pc[2] | F.pc[2] | D_readygo | D_readygo1)

11
src/Core/Gadgets.sv
View File

@ -98,16 +98,17 @@ module woutput (
error = (addr != 2'b00); error = (addr != 2'b00);
end end
2'b01: begin 2'b01: begin
wdata = addr[1] ? data[31:16] : data[15:0]; wdata = {2{data[15:0]}};
wstrb = addr[1] ? 4'b1100 : 4'b0011; wstrb = addr[1] ? 4'b1100 : 4'b0011;
error = (addr[0] != 1'b0); error = (addr[0] != 1'b0);
end end
2'b00: begin 2'b00: begin
wdata = {4{data[7:0]}};
case (addr) case (addr)
2'b11: begin wdata = data[31:24]; wstrb = 4'b1000; end 2'b11: wstrb = 4'b1000;
2'b10: begin wdata = data[23:16]; wstrb = 4'b0100; end 2'b10: wstrb = 4'b0100;
2'b01: begin wdata = data[15: 8]; wstrb = 4'b0010; end 2'b01: wstrb = 4'b0010;
2'b00: begin wdata = data[ 7: 0]; wstrb = 4'b0001; end 2'b00: wstrb = 4'b0001;
endcase endcase
error = 1'b0; error = 1'b0;
end end