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fix?

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fix typo

fix mult
This commit is contained in:
Paul Pan 2021-08-01 22:24:19 +08:00
parent 8de814d26e
commit f137fd434f
4 changed files with 16 additions and 25 deletions
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29
src/Core/Datapath.sv
View File

@ -700,16 +700,16 @@ module Datapath (
); );
// E.I0.MUL // E.I0.MUL
assign E_I0_MULDIV_req = ~E.I0.MCtrl.HLS[2] & E_I0_go & M.en & ~rstM; assign E_I0_MULDIV_req = (E.I0.MCtrl.HW & E.I0.MCtrl.LW) & E_I0_go & M.en & ~rstM;
mul_signed E_I0_MULT_Signed ( mul_signed E_I0_MULT_Signed (
.clk(clk), .CLK(clk),
.A (E_I0_ForwardS), .A (E_I0_ForwardS),
.B (E_I0_ForwardT), .B (E_I0_ForwardT),
.P ({M_I0_MULTH, M_I0_MULTL}) .P ({M_I0_MULTH, M_I0_MULTL})
); );
mul_signed E_I0_MULTU_Signed ( mul_signed E_I0_MULTU_Signed (
.clk(clk), .CLK(clk),
.A (E_I0_ForwardS), .A (E_I0_ForwardS),
.B (E_I0_ForwardT), .B (E_I0_ForwardT),
.P ({M_I0_MULTUH, M_I0_MULTUL}) .P ({M_I0_MULTUH, M_I0_MULTUL})
@ -884,6 +884,14 @@ module Datapath (
~E_go | ~E_I0_go, ~E_go | ~E_I0_go,
{M.I0.RD, M.I0.WCtrl} {M.I0.RD, M.I0.WCtrl}
); );
ffenrc #(5) M_I0_MULT_CNTR_ff (
clk,
rst | rstM,
{E_I0_MULDIV_req, M_I0_MULT_CNTR[4:1]},
1'b1,
~E_go | ~E_I0_go,
M_I0_MULT_CNTR
);
ffen #(32) M_I1_pc_ff ( ffen #(32) M_I1_pc_ff (
clk, clk,
E.I1.pc, E.I1.pc,
@ -920,12 +928,6 @@ module Datapath (
~E_go | ~E_I1_go, ~E_go | ~E_I1_go,
{M.I1.RD, M.I1.WCtrl} {M.I1.RD, M.I1.WCtrl}
); );
ffen #(5) M_I0_MULT_CNTR_ff (
clk,
{E_I0_MULDIV_req, M_I0_MULT_CNTR[4:1]},
1'b1,
M_I0_MULT_CNTR
);
// M.Exc // M.Exc
assign M.I0.BadVAddr = M.I0.pc; assign M.I0.BadVAddr = M.I0.pc;
@ -958,7 +960,7 @@ module Datapath (
{M_I0_MULTL, M_I0_MULTH}, {M_I0_MULTL, M_I0_MULTH},
M.en, M.en,
M_I0_MULTU_bvalid, M_I0_MULTU_bvalid,
{M_I0_MULTLB, M_I0_MULTHB} {M_I0_MULTULB, M_I0_MULTUHB}
); );
// M.I0.DIV // M.I0.DIV
@ -1072,11 +1074,8 @@ module Datapath (
); );
assign M.en = M_go & W.en; assign M.en = M_go & W.en;
assign M_go = (~M.I1.MCtrl.MR | M_I1_DataR_OK) assign M_go = (~(M.I0.MCtrl.HW & M.I0.MCtrl.LW) | M_I0_DIV_bvalid & M_I0_DIVU_bvalid & M_I0_MULT_bvalid & M_I0_MULTU_bvalid)
& (M.I0.MCtrl.HLS != DIV | M_I0_DIV_bvalid) & (~M.I1.MCtrl.MR | M_I1_DataR_OK)
& (M.I0.MCtrl.HLS != DIVU | M_I0_DIVU_bvalid)
& (M.I0.MCtrl.HLS != MULT | M_I0_MULT_bvalid)
& (M.I0.MCtrl.HLS != MULTU | M_I0_MULTU_bvalid)
& (~M_exception.ExcValid | fetch_i.req & fetch_i.addr_ok); & (~M_exception.ExcValid | fetch_i.req & fetch_i.addr_ok);
// M.Forwarding // M.Forwarding

8
src/include/defines.svh
View File

@ -235,10 +235,6 @@ typedef struct packed {
ECtrl_t ECtrl; ECtrl_t ECtrl;
word_t ALUOut; word_t ALUOut;
// word_t MULTH, MULTL;
// word_t MULTUH, MULTUL;
// word_t DIVH, DIVL;
// word_t DIVUH, DIVUL;
MCtrl0_t MCtrl; MCtrl0_t MCtrl;
@ -293,10 +289,6 @@ typedef struct packed {
word_t T; word_t T;
word_t ALUOut; word_t ALUOut;
word_t MULTH, MULTL;
word_t MULTUH, MULTUL;
word_t DIVH, DIVL;
word_t DIVUH, DIVUL;
MCtrl0_t MCtrl; MCtrl0_t MCtrl;
word_t RDataW; word_t RDataW;

2
src/testbench/happy/mul_signed.sv
View File

@ -1,7 +1,7 @@
// Make Linter Happy // Make Linter Happy
module mul_signed ( module mul_signed (
input clk, input CLK,
input [31:0] A, input [31:0] A,
input [31:0] B, input [31:0] B,
output [63:0] P output [63:0] P

2
src/testbench/happy/mul_unsigned.sv
View File

@ -1,7 +1,7 @@
// Make Linter Happy // Make Linter Happy
module mul_unsigned ( module mul_unsigned (
input clk, input CLK,
input [31:0] A, input [31:0] A,
input [31:0] B, input [31:0] B,
output [63:0] P output [63:0] P