diff --git a/src/Core/Datapath.sv b/src/Core/Datapath.sv
index 2b5ce4c..e6140f3 100644
--- a/src/Core/Datapath.sv
+++ b/src/Core/Datapath.sv
@@ -700,16 +700,16 @@ module Datapath (
   );
 
   // E.I0.MUL
-  assign E_I0_MULDIV_req = ~E.I0.MCtrl.HLS[2] & E_I0_go & M.en & ~rstM;
+  assign E_I0_MULDIV_req = (E.I0.MCtrl.HW & E.I0.MCtrl.LW) & E_I0_go & M.en & ~rstM;
 
   mul_signed E_I0_MULT_Signed (
-      .clk(clk),
+      .CLK(clk),
       .A  (E_I0_ForwardS),
       .B  (E_I0_ForwardT),
       .P  ({M_I0_MULTH, M_I0_MULTL})
   );
   mul_signed E_I0_MULTU_Signed (
-      .clk(clk),
+      .CLK(clk),
       .A  (E_I0_ForwardS),
       .B  (E_I0_ForwardT),
       .P  ({M_I0_MULTUH, M_I0_MULTUL})
@@ -884,6 +884,14 @@ module Datapath (
       ~E_go | ~E_I0_go,
       {M.I0.RD, M.I0.WCtrl}
   );
+  ffenrc #(5) M_I0_MULT_CNTR_ff (
+      clk,
+      rst | rstM,
+      {E_I0_MULDIV_req, M_I0_MULT_CNTR[4:1]},
+      1'b1,
+      ~E_go | ~E_I0_go,
+      M_I0_MULT_CNTR
+  );
   ffen #(32) M_I1_pc_ff (
       clk,
       E.I1.pc,
@@ -920,12 +928,6 @@ module Datapath (
       ~E_go | ~E_I1_go,
       {M.I1.RD, M.I1.WCtrl}
   );
-  ffen #(5) M_I0_MULT_CNTR_ff (
-      clk,
-      {E_I0_MULDIV_req, M_I0_MULT_CNTR[4:1]},
-      1'b1,
-      M_I0_MULT_CNTR
-  );
 
   // M.Exc
   assign M.I0.BadVAddr = M.I0.pc;
@@ -958,7 +960,7 @@ module Datapath (
       {M_I0_MULTL, M_I0_MULTH},
       M.en,
       M_I0_MULTU_bvalid,
-      {M_I0_MULTLB, M_I0_MULTHB}
+      {M_I0_MULTULB, M_I0_MULTUHB}
   );
 
   // M.I0.DIV
@@ -1072,11 +1074,8 @@ module Datapath (
   );
 
   assign M.en = M_go & W.en;
-  assign M_go = (~M.I1.MCtrl.MR | M_I1_DataR_OK)
-              & (M.I0.MCtrl.HLS != DIV   | M_I0_DIV_bvalid)
-              & (M.I0.MCtrl.HLS != DIVU  | M_I0_DIVU_bvalid)
-              & (M.I0.MCtrl.HLS != MULT  | M_I0_MULT_bvalid)
-              & (M.I0.MCtrl.HLS != MULTU | M_I0_MULTU_bvalid)
+  assign M_go = (~(M.I0.MCtrl.HW & M.I0.MCtrl.LW) | M_I0_DIV_bvalid & M_I0_DIVU_bvalid & M_I0_MULT_bvalid & M_I0_MULTU_bvalid)
+              & (~M.I1.MCtrl.MR | M_I1_DataR_OK)
               & (~M_exception.ExcValid | fetch_i.req & fetch_i.addr_ok);
 
   // M.Forwarding
diff --git a/src/include/defines.svh b/src/include/defines.svh
index b3b1880..9eb440f 100644
--- a/src/include/defines.svh
+++ b/src/include/defines.svh
@@ -235,10 +235,6 @@ typedef struct packed {
 
     ECtrl_t ECtrl;
     word_t  ALUOut;
-    // word_t  MULTH,  MULTL;
-    // word_t  MULTUH, MULTUL;
-    // word_t  DIVH,   DIVL;
-    // word_t  DIVUH,  DIVUL;
 
     MCtrl0_t MCtrl;
 
@@ -293,10 +289,6 @@ typedef struct packed {
     word_t      T;
 
     word_t ALUOut;
-    word_t MULTH,  MULTL;
-    word_t MULTUH, MULTUL;
-    word_t DIVH,   DIVL;
-    word_t DIVUH,  DIVUL;
 
     MCtrl0_t MCtrl;
     word_t   RDataW;
diff --git a/src/testbench/happy/mul_signed.sv b/src/testbench/happy/mul_signed.sv
index 9e65bb4..80e31c0 100644
--- a/src/testbench/happy/mul_signed.sv
+++ b/src/testbench/happy/mul_signed.sv
@@ -1,7 +1,7 @@
 // Make Linter Happy
 
 module mul_signed (
-    input         clk,
+    input         CLK,
     input  [31:0] A,
     input  [31:0] B,
     output [63:0] P
diff --git a/src/testbench/happy/mul_unsigned.sv b/src/testbench/happy/mul_unsigned.sv
index e1ae693..44cc10b 100644
--- a/src/testbench/happy/mul_unsigned.sv
+++ b/src/testbench/happy/mul_unsigned.sv
@@ -1,7 +1,7 @@
 // Make Linter Happy
 
 module mul_unsigned (
-    input         clk,
+    input         CLK,
     input  [31:0] A,
     input  [31:0] B,
     output [63:0] P