Update Simulation Scripts
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2bba9311e3
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12
sim/Makefile
12
sim/Makefile
@ -8,14 +8,13 @@ VERILATOR_COVERAGE = verilator_coverage
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####################
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####################
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# Flags #
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# Flags #
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####################
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####################
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VERILATOR_BUILD_FLAGS += -cc --exe
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VERILATOR_BUILD_FLAGS += -cc --exe --timing
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VERILATOR_BUILD_FLAGS += -MMD
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VERILATOR_BUILD_FLAGS += -MMD
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VERILATOR_BUILD_FLAGS += -O3 --x-assign fast --x-initial fast -CFLAGS -O3
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VERILATOR_BUILD_FLAGS += -O3 --x-assign unique --x-initial unique
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VERILATOR_BUILD_FLAGS += -Wall
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VERILATOR_BUILD_FLAGS += -Wall -Wpedantic
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VERILATOR_BUILD_FLAGS += --trace --trace-fst --trace-params --trace-structs --trace-underscore
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VERILATOR_BUILD_FLAGS += --trace --trace-fst --trace-params --trace-structs --trace-underscore
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VERILATOR_BUILD_FLAGS += --assert
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VERILATOR_BUILD_FLAGS += --assert
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VERILATOR_BUILD_FLAGS += --coverage
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VERILATOR_BUILD_FLAGS += --coverage
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VERILATOR_BUILD_FLAGS += -CFLAGS "-Wno-parentheses-equality" -j
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#VERILATOR_BUILD_FLAGS += --report-unoptflat
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#VERILATOR_BUILD_FLAGS += --report-unoptflat
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VERILATOR_COV_FLAGS += --annotate logs/annotated
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VERILATOR_COV_FLAGS += --annotate logs/annotated
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@ -50,11 +49,14 @@ verilate:
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func_soft:
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func_soft:
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cd ../resources/soft/func && make clean && make && cp obj/inst_ram.mif ../../../sim && cp obj/data_ram.mif ../../../sim && cd ../../../sim
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cd ../resources/soft/func && make clean && make && cp obj/inst_ram.mif ../../../sim && cp obj/data_ram.mif ../../../sim && cd ../../../sim
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perf_soft:
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cd ../resources/soft/perf_func && make clean && make && cp obj/allbench/axi_ram.mif ../../../sim && cd ../../../sim && mv axi_ram.mif inst_ram.mif
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tlb_soft:
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tlb_soft:
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cd ../resources/soft/tlb_func && make clean && make && cp obj/inst_ram.mif ../../../sim && cp obj/data_ram.mif ../../../sim && cd ../../../sim
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cd ../resources/soft/tlb_func && make clean && make && cp obj/inst_ram.mif ../../../sim && cp obj/data_ram.mif ../../../sim && cd ../../../sim
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build: verilate
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build: verilate
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make -C obj_dir -f Vtestbench_top.mk -j 10
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make -C obj_dir -f Vtestbench_top.mk -j `nproc`
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coverage:
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coverage:
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@rm -rf logs/annotated
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@rm -rf logs/annotated
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@ -157,13 +157,16 @@ initial begin
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$display("[%0t] ram[0x3f00001] = 0x%0h", $time, mem['h3f00001]);
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$display("[%0t] ram[0x3f00001] = 0x%0h", $time, mem['h3f00001]);
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$display("[%0t] ram[0x3f00002] = 0x%0h", $time, mem['h3f00002]);
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$display("[%0t] ram[0x3f00002] = 0x%0h", $time, mem['h3f00002]);
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$display("[%0t] ram[0x40] = 0x%0h", $time, mem['h40]);
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$display("[%0t] ram[0x40] = 0x%0h", $time, mem['h40]);
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$display("[%0t] ram[0x1000000] = 0x%0h", $time, mem['h1000000]);
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$display("[%0t] ram[0x1000001] = 0x%0h", $time, mem['h1000001]);
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$display("[%0t] ram[0x1000002] = 0x%0h", $time, mem['h1000002]);
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end
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end
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reg [31:0] trace_before = 0;
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reg [31:0] trace_before = 0;
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always @(posedge s_aclk) begin
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always @(posedge s_aclk) begin
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if (mem['h1000000] != trace_before) begin
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if (mem['h1000000] != trace_before) begin
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trace_before <= mem['h1000000];
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trace_before <= mem['h1000000];
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$display("[%0t] ram['h1000000] = 0x%0h, before = 0x%0h", $time, mem['h1000000], trace_before);
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$display("[%0t] ram[0x1000000] = 0x%0h, before = 0x%0h", $time, mem['h1000000], trace_before);
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end
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end
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end
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end
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@ -17,6 +17,10 @@ int main(int argc, char **argv, char **env) {
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ctrl_c_hit = false;
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ctrl_c_hit = false;
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signal(SIGINT, ctrl_c_handler);
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signal(SIGINT, ctrl_c_handler);
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unsigned int switch_sim = 0;
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if (argc > 1)
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switch_sim = atoi(argv[1]);
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Verilated::commandArgs(argc, argv);
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Verilated::commandArgs(argc, argv);
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Verilated::randReset(2);
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Verilated::randReset(2);
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Verilated::traceEverOn(true);
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Verilated::traceEverOn(true);
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@ -30,7 +34,7 @@ int main(int argc, char **argv, char **env) {
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std::cout << "<<< Simulation Started >>>" << std::endl;
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std::cout << "<<< Simulation Started >>>" << std::endl;
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auto time_start = std::chrono::high_resolution_clock::now();
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auto time_start = std::chrono::high_resolution_clock::now();
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top->clk = 0;
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top->clk = 0;
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top->switch_sim = ~(0);
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top->switch_sim = ~switch_sim;
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while (!Verilated::gotFinish() && main_time < time_limit) {
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while (!Verilated::gotFinish() && main_time < time_limit) {
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if (ctrl_c_hit)
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if (ctrl_c_hit)
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break;
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break;
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@ -38,8 +42,11 @@ int main(int argc, char **argv, char **env) {
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++main_time;
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++main_time;
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top->clk = !top->clk;
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top->clk = !top->clk;
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top->resetn = (main_time < reset_time) ? 0 : 1;
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top->resetn = (main_time < reset_time) ? 0 : 1;
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#if VM_COVERAGE
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if (main_time < reset_time)
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if (main_time < reset_time)
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VerilatedCov::zero();
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VerilatedCov::zero();
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#endif
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top->eval();
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top->eval();
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}
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}
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