From f0e20f43376b23963f0d96ed7b724c94b1552f6d Mon Sep 17 00:00:00 2001
From: Paul Pan <i@0x7f.app>
Date: Wed, 10 Jan 2024 22:02:49 +0800
Subject: [PATCH] Update Simulation Scripts

---
 sim/Makefile        | 12 +++++++-----
 sim/model/axi_ram.v |  5 ++++-
 sim/sim_main.cpp    |  9 ++++++++-
 3 files changed, 19 insertions(+), 7 deletions(-)

diff --git a/sim/Makefile b/sim/Makefile
index 260e1a7..a995d2e 100644
--- a/sim/Makefile
+++ b/sim/Makefile
@@ -8,14 +8,13 @@ VERILATOR_COVERAGE = verilator_coverage
 ####################
 #       Flags      #
 ####################
-VERILATOR_BUILD_FLAGS += -cc --exe
+VERILATOR_BUILD_FLAGS += -cc --exe --timing
 VERILATOR_BUILD_FLAGS += -MMD
-VERILATOR_BUILD_FLAGS += -O3 --x-assign fast --x-initial fast -CFLAGS -O3
-VERILATOR_BUILD_FLAGS += -Wall
+VERILATOR_BUILD_FLAGS += -O3 --x-assign unique --x-initial unique
+VERILATOR_BUILD_FLAGS += -Wall -Wpedantic
 VERILATOR_BUILD_FLAGS += --trace --trace-fst --trace-params --trace-structs --trace-underscore
 VERILATOR_BUILD_FLAGS += --assert
 VERILATOR_BUILD_FLAGS += --coverage
-VERILATOR_BUILD_FLAGS += -CFLAGS "-Wno-parentheses-equality" -j
 #VERILATOR_BUILD_FLAGS += --report-unoptflat
 
 VERILATOR_COV_FLAGS += --annotate logs/annotated
@@ -50,11 +49,14 @@ verilate:
 func_soft:
 	cd ../resources/soft/func && make clean && make && cp obj/inst_ram.mif ../../../sim && cp obj/data_ram.mif ../../../sim && cd ../../../sim
 
+perf_soft:
+	cd ../resources/soft/perf_func && make clean && make && cp obj/allbench/axi_ram.mif ../../../sim && cd ../../../sim && mv axi_ram.mif inst_ram.mif
+
 tlb_soft:
 	cd ../resources/soft/tlb_func && make clean && make && cp obj/inst_ram.mif ../../../sim && cp obj/data_ram.mif ../../../sim && cd ../../../sim
 
 build: verilate
-	make -C obj_dir -f Vtestbench_top.mk -j 10
+	make -C obj_dir -f Vtestbench_top.mk -j `nproc`
 
 coverage:
 	@rm -rf logs/annotated
diff --git a/sim/model/axi_ram.v b/sim/model/axi_ram.v
index f9b999d..8bed520 100644
--- a/sim/model/axi_ram.v
+++ b/sim/model/axi_ram.v
@@ -157,13 +157,16 @@ initial begin
   $display("[%0t] ram[0x3f00001] = 0x%0h", $time, mem['h3f00001]);
   $display("[%0t] ram[0x3f00002] = 0x%0h", $time, mem['h3f00002]);
   $display("[%0t] ram[0x40] = 0x%0h", $time, mem['h40]);
+  $display("[%0t] ram[0x1000000] = 0x%0h", $time, mem['h1000000]);
+  $display("[%0t] ram[0x1000001] = 0x%0h", $time, mem['h1000001]);
+  $display("[%0t] ram[0x1000002] = 0x%0h", $time, mem['h1000002]);
 end
 
 reg [31:0] trace_before = 0;
 always @(posedge s_aclk) begin
     if (mem['h1000000] != trace_before) begin
         trace_before <= mem['h1000000];
-        $display("[%0t] ram['h1000000] = 0x%0h, before = 0x%0h", $time, mem['h1000000], trace_before);
+        $display("[%0t] ram[0x1000000] = 0x%0h, before = 0x%0h", $time, mem['h1000000], trace_before);
     end
 end
 
diff --git a/sim/sim_main.cpp b/sim/sim_main.cpp
index d0ba72a..b550416 100644
--- a/sim/sim_main.cpp
+++ b/sim/sim_main.cpp
@@ -17,6 +17,10 @@ int main(int argc, char **argv, char **env) {
     ctrl_c_hit = false;
     signal(SIGINT, ctrl_c_handler);
 
+    unsigned int switch_sim = 0;
+    if (argc > 1)
+        switch_sim = atoi(argv[1]);
+
     Verilated::commandArgs(argc, argv);
     Verilated::randReset(2);
     Verilated::traceEverOn(true);
@@ -30,7 +34,7 @@ int main(int argc, char **argv, char **env) {
     std::cout << "<<< Simulation Started >>>" << std::endl;
     auto time_start = std::chrono::high_resolution_clock::now();
     top->clk = 0;
-    top->switch_sim = ~(0);
+    top->switch_sim = ~switch_sim;
     while (!Verilated::gotFinish() && main_time < time_limit) {
         if (ctrl_c_hit)
             break;
@@ -38,8 +42,11 @@ int main(int argc, char **argv, char **env) {
         ++main_time;
         top->clk = !top->clk;
         top->resetn = (main_time < reset_time) ? 0 : 1;
+
+#if VM_COVERAGE
         if (main_time < reset_time)
             VerilatedCov::zero();
+#endif
 
         top->eval();
     }