add lwl lwr swl swr test cases
This commit is contained in:
parent
cf9d3e8ed0
commit
eea7b6bbda
@ -4,6 +4,7 @@
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`define TRACE_REF_FILE "../../../../../../../cpu132_gettrace/golden_trace.txt"
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`define CONFREG_NUM_REG soc_lite.u_confreg.num_data
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`define CONFREG_OPEN_TRACE soc_lite.u_confreg.open_trace
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//`define CONFREG_OPEN_TRACE 1'b0
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`define CONFREG_NUM_MONITOR soc_lite.u_confreg.num_monitor
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`define CONFREG_UART_DISPLAY soc_lite.u_confreg.write_uart_valid
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`define CONFREG_UART_DATA soc_lite.u_confreg.write_uart_data
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@ -84,11 +85,11 @@ module tb2_top ();
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assign debug_wb_rf_wen = soc_lite.debug_wb_rf_wen;
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assign debug_wb_rf_wnum = soc_lite.debug_wb_rf_wnum;
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assign debug_wb_rf_wdata = soc_lite.debug_wb_rf_wdata;
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assign debug_wb1_pc = soc_lite.debug_wb1_pc;
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assign debug_wb1_rf_wen = soc_lite.debug_wb1_rf_wen;
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assign debug_wb1_rf_wnum = soc_lite.debug_wb1_rf_wnum;
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assign debug_wb1_rf_wdata = soc_lite.debug_wb1_rf_wdata;
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assign debug_wb_pc_A = soc_lite.debug_wb_pc_A;
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assign debug_wb1_pc = soc_lite.u_cpu.debug_wb1_pc;
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assign debug_wb1_rf_wen = soc_lite.u_cpu.debug_wb1_rf_wen;
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assign debug_wb1_rf_wnum = soc_lite.u_cpu.debug_wb1_rf_wnum;
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assign debug_wb1_rf_wdata = soc_lite.u_cpu.debug_wb1_rf_wdata;
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assign debug_wb_pc_A = soc_lite.u_cpu.debug_wb_pc_A;
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// open the trace file;
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integer trace_ref;
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@ -145,7 +146,7 @@ module tb2_top ();
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#2;
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if (!resetn) begin
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debug_wb_err <= 1'b0;
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end else if (!debug_end && `CONFREG_OPEN_TRACE) begin
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end else if (!debug_end) begin
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if (debug_wb_pc_A) begin
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dbg_0_rf_wen <= debug_wb1_rf_wen;
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dbg_0_pc <= debug_wb1_pc;
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@ -177,7 +178,7 @@ module tb2_top ();
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dbg_1_pc, dbg_1_rf_wnum, dbg_1_rf_wdata, |dbg_1_rf_wen);
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end
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if (|dbg_0_rf_wen && dbg_0_rf_wnum != 5'd0) begin
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if (|dbg_0_rf_wen && dbg_0_rf_wnum != 5'd0 && `CONFREG_OPEN_TRACE) begin
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if ( (dbg_0_pc !== ref_trace[0].ref_wb_pc )
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|| (dbg_0_rf_wnum !== ref_trace[0].ref_wb_rf_wnum )
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|| (dbg_0_rf_wdata !== ref_trace[0].ref_wb_rf_wdata)
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@ -198,7 +199,7 @@ module tb2_top ();
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$finish;
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end else ref_trace.pop_front();
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end
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if (|dbg_1_rf_wen && dbg_1_rf_wnum != 5'd0) begin
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if (|dbg_1_rf_wen && dbg_1_rf_wnum != 5'd0 && `CONFREG_OPEN_TRACE) begin
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if ( (dbg_1_pc !== ref_trace[0].ref_wb_pc )
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|| (dbg_1_rf_wnum !== ref_trace[0].ref_wb_rf_wnum )
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|| (dbg_1_rf_wdata !== ref_trace[0].ref_wb_rf_wdata)
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@ -266,7 +267,7 @@ module tb2_top ();
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end
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end
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//妯℃嫙涓插彛鎵撳嵃
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// Uart Display
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logic uart_display;
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logic [7:0] uart_data;
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assign uart_display = `CONFREG_UART_DISPLAY;
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@ -1290,3 +1290,49 @@
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mtc0 v1, c0_cause; \
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1: b 1b; \
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nop
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/*90*/
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#define TEST_LWL(data, base_addr, offset, offset_align, ref, confuse) \
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LI(t1, data); \
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LI(t0, base_addr); \
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LI(v1, ref); \
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LI(v0, confuse); \
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sw t1, offset_align(t0); \
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lwl v0, offset(t0); \
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bne v0, v1, inst_error; \
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nop
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/*91*/
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#define TEST_LWR(data, base_addr, offset, offset_align, ref, confuse) \
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LI(t1, data); \
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LI(t0, base_addr); \
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LI(v1, ref); \
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LI(v0, confuse); \
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sw t1, offset_align(t0); \
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lwr v0, offset(t0); \
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bne v0, v1, inst_error; \
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nop
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/*92*/
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#define TEST_SWL(data, base_addr, offset, offset_align, ref, confuse) \
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LI(t1, data); \
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LI(t0, base_addr); \
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LI(v0, confuse); \
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LI(v1, ref); \
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sw v0, offset_align(t0); \
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swl t1, offset(t0); \
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lw v0, offset_align(t0); \
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bne v0, v1, inst_error; \
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nop
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/*93*/
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#define TEST_SWR(data, base_addr, offset, offset_align, ref, confuse) \
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LI(t1, data); \
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LI(t0, base_addr); \
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LI(v0, confuse); \
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LI(v1, ref); \
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sw v0, offset_align(t0); \
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swr t1, offset(t0); \
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lw v0, offset_align(t0); \
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bne v0, v1, inst_error; \
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nop
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41
resources/2021/soft/func/inst/n90_lwl.S
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resources/2021/soft/func/inst/n90_lwl.S
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@ -0,0 +1,41 @@
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#include <asm.h>
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#include <regdef.h>
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#include <inst_test.h>
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LEAF(n90_lwl_test)
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.set noreorder
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addiu s0, s0 ,1
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li s2, 0x0
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###test inst
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TEST_LWL(0xc822c7e8, 0x800d34c0, 0x000066a8, 0x000066a8, 0xE8B6C7D8, 0xA5B6C7D8)
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TEST_LWL(0xc822c7e8, 0x800d34c0, 0x000066a9, 0x000066a8, 0xC7E8C7D8, 0xA5B6C7D8)
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TEST_LWL(0xc822c7e8, 0x800d34c0, 0x000066aA, 0x000066a8, 0x22C7E8D8, 0xA5B6C7D8)
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TEST_LWL(0xc822c7e8, 0x800d34c0, 0x000066aB, 0x000066a8, 0xC822C7E8, 0xA5B6C7D8)
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TEST_LWL(0x71737c10, 0x800df660, 0x000002e4, 0x000002e4, 0x10B6C7D8, 0xA5B6C7D8)
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TEST_LWL(0x71737c10, 0x800df660, 0x000002e5, 0x000002e4, 0x7C10C7D8, 0xA5B6C7D8)
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TEST_LWL(0x71737c10, 0x800df660, 0x000002e6, 0x000002e4, 0x737C10D8, 0xA5B6C7D8)
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TEST_LWL(0x71737c10, 0x800df660, 0x000002e7, 0x000002e4, 0x71737C10, 0xA5B6C7D8)
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TEST_LWL(0x03682420, 0x800d24e4, 0x00001680, 0x00001680, 0x20B6C7D8, 0xA5B6C7D8)
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TEST_LWL(0x03682420, 0x800d24e4, 0x00001681, 0x00001680, 0x2420C7D8, 0xA5B6C7D8)
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TEST_LWL(0x03682420, 0x800d24e4, 0x00001682, 0x00001680, 0x682420D8, 0xA5B6C7D8)
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TEST_LWL(0x03682420, 0x800d24e4, 0x00001683, 0x00001680, 0x03682420, 0xA5B6C7D8)
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TEST_LWL(0x6f59f5d3, 0x800dabdc, 0x000001b0, 0x000001b0, 0xd3B6C7D8, 0xA5B6C7D8)
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TEST_LWL(0x6f59f5d3, 0x800dabdc, 0x000001b1, 0x000001b0, 0xf5d3C7D8, 0xA5B6C7D8)
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TEST_LWL(0x6f59f5d3, 0x800dabdc, 0x000001b2, 0x000001b0, 0x59f5d3D8, 0xA5B6C7D8)
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TEST_LWL(0x6f59f5d3, 0x800dabdc, 0x000001b3, 0x000001b0, 0x6f59f5d3, 0xA5B6C7D8)
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###detect exception
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bne s2, zero, inst_error
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nop
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###score ++
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addiu s3, s3, 1
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###output (s0<<24)|s3
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inst_error:
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sll t1, s0, 24
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or t0, t1, s3
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sw t0, 0(s1)
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jr ra
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nop
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END(n90_lwl_test)
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resources/2021/soft/func/inst/n91_lwr.S
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resources/2021/soft/func/inst/n91_lwr.S
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@ -0,0 +1,41 @@
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#include <asm.h>
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#include <regdef.h>
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#include <inst_test.h>
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LEAF(n91_lwr_test)
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.set noreorder
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addiu s0, s0 ,1
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li s2, 0x0
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###test inst
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TEST_LWR(0xc822c7e8, 0x800d34c0, 0x000066a8, 0x000066a8, 0xc822c7e8, 0xA5B6C7D8)
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TEST_LWR(0xc822c7e8, 0x800d34c0, 0x000066a9, 0x000066a8, 0xA5c822c7, 0xA5B6C7D8)
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TEST_LWR(0xc822c7e8, 0x800d34c0, 0x000066aA, 0x000066a8, 0xA5B6c822, 0xA5B6C7D8)
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TEST_LWR(0xc822c7e8, 0x800d34c0, 0x000066aB, 0x000066a8, 0xA5B6C7c8, 0xA5B6C7D8)
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TEST_LWR(0x71737c10, 0x800df660, 0x000002e4, 0x000002e4, 0x71737c10, 0xA5B6C7D8)
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TEST_LWR(0x71737c10, 0x800df660, 0x000002e5, 0x000002e4, 0xA571737c, 0xA5B6C7D8)
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TEST_LWR(0x71737c10, 0x800df660, 0x000002e6, 0x000002e4, 0xA5B67173, 0xA5B6C7D8)
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TEST_LWR(0x71737c10, 0x800df660, 0x000002e7, 0x000002e4, 0xA5B6C771, 0xA5B6C7D8)
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TEST_LWR(0x03682420, 0x800d24e4, 0x00001680, 0x00001680, 0x03682420, 0xA5B6C7D8)
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TEST_LWR(0x03682420, 0x800d24e4, 0x00001681, 0x00001680, 0xA5036824, 0xA5B6C7D8)
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TEST_LWR(0x03682420, 0x800d24e4, 0x00001682, 0x00001680, 0xA5B60368, 0xA5B6C7D8)
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TEST_LWR(0x03682420, 0x800d24e4, 0x00001683, 0x00001680, 0xA5B6C703, 0xA5B6C7D8)
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TEST_LWR(0x6f59f5d3, 0x800dabdc, 0x000001b0, 0x000001b0, 0x6f59f5d3, 0xA5B6C7D8)
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TEST_LWR(0x6f59f5d3, 0x800dabdc, 0x000001b1, 0x000001b0, 0xA56f59f5, 0xA5B6C7D8)
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TEST_LWR(0x6f59f5d3, 0x800dabdc, 0x000001b2, 0x000001b0, 0xA5B66f59, 0xA5B6C7D8)
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TEST_LWR(0x6f59f5d3, 0x800dabdc, 0x000001b3, 0x000001b0, 0xA5B6C76f, 0xA5B6C7D8)
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###detect exception
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bne s2, zero, inst_error
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nop
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###score ++
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addiu s3, s3, 1
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###output (s0<<24)|s3
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inst_error:
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sll t1, s0, 24
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or t0, t1, s3
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sw t0, 0(s1)
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jr ra
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nop
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END(n91_lwr_test)
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resources/2021/soft/func/inst/n92_swl.S
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resources/2021/soft/func/inst/n92_swl.S
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@ -0,0 +1,41 @@
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#include <asm.h>
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#include <regdef.h>
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#include <inst_test.h>
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LEAF(n92_swl_test)
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.set noreorder
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addiu s0, s0 ,1
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li s2, 0x0
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###test inst
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TEST_SWL(0xc822c7e8, 0x800d34c0, 0x000066a8, 0x000066a8, 0xA5B6C7c8, 0xA5B6C7D8)
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TEST_SWL(0xc822c7e8, 0x800d34c0, 0x000066a9, 0x000066a8, 0xA5B6c822, 0xA5B6C7D8)
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TEST_SWL(0xc822c7e8, 0x800d34c0, 0x000066aA, 0x000066a8, 0xA5c822c7, 0xA5B6C7D8)
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TEST_SWL(0xc822c7e8, 0x800d34c0, 0x000066aB, 0x000066a8, 0xc822c7e8, 0xA5B6C7D8)
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TEST_SWL(0x71737c10, 0x800df660, 0x000002e4, 0x000002e4, 0xA5B6C771, 0xA5B6C7D8)
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TEST_SWL(0x71737c10, 0x800df660, 0x000002e5, 0x000002e4, 0xA5B67173, 0xA5B6C7D8)
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TEST_SWL(0x71737c10, 0x800df660, 0x000002e6, 0x000002e4, 0xA571737c, 0xA5B6C7D8)
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TEST_SWL(0x71737c10, 0x800df660, 0x000002e7, 0x000002e4, 0x71737c10, 0xA5B6C7D8)
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TEST_SWL(0x03682420, 0x800d24e4, 0x00001680, 0x00001680, 0xA5B6C703, 0xA5B6C7D8)
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TEST_SWL(0x03682420, 0x800d24e4, 0x00001681, 0x00001680, 0xA5B60368, 0xA5B6C7D8)
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TEST_SWL(0x03682420, 0x800d24e4, 0x00001682, 0x00001680, 0xA5036824, 0xA5B6C7D8)
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TEST_SWL(0x03682420, 0x800d24e4, 0x00001683, 0x00001680, 0x03682420, 0xA5B6C7D8)
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TEST_SWL(0x6f59f5d3, 0x800dabdc, 0x000001b0, 0x000001b0, 0xA5B6C76f, 0xA5B6C7D8)
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TEST_SWL(0x6f59f5d3, 0x800dabdc, 0x000001b1, 0x000001b0, 0xA5B66f59, 0xA5B6C7D8)
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TEST_SWL(0x6f59f5d3, 0x800dabdc, 0x000001b2, 0x000001b0, 0xA56f59f5, 0xA5B6C7D8)
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TEST_SWL(0x6f59f5d3, 0x800dabdc, 0x000001b3, 0x000001b0, 0x6f59f5d3, 0xA5B6C7D8)
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###detect exception
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bne s2, zero, inst_error
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nop
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###score ++
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addiu s3, s3, 1
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###output (s0<<24)|s3
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inst_error:
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sll t1, s0, 24
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or t0, t1, s3
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sw t0, 0(s1)
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jr ra
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nop
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END(n92_swl_test)
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41
resources/2021/soft/func/inst/n93_swr.S
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41
resources/2021/soft/func/inst/n93_swr.S
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#include <asm.h>
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#include <regdef.h>
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#include <inst_test.h>
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LEAF(n93_swr_test)
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.set noreorder
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addiu s0, s0 ,1
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li s2, 0x0
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###test inst
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TEST_SWR(0xc822c7e8, 0x800d34c0, 0x000066a8, 0x000066a8, 0xc822c7e8, 0xA5B6C7D8)
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TEST_SWR(0xc822c7e8, 0x800d34c0, 0x000066a9, 0x000066a8, 0x22c7e8D8, 0xA5B6C7D8)
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TEST_SWR(0xc822c7e8, 0x800d34c0, 0x000066aA, 0x000066a8, 0xc7e8C7D8, 0xA5B6C7D8)
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TEST_SWR(0xc822c7e8, 0x800d34c0, 0x000066aB, 0x000066a8, 0xe8B6C7D8, 0xA5B6C7D8)
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TEST_SWR(0x71737c10, 0x800df660, 0x000002e4, 0x000002e4, 0x71737c10, 0xA5B6C7D8)
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TEST_SWR(0x71737c10, 0x800df660, 0x000002e5, 0x000002e4, 0x737c10D8, 0xA5B6C7D8)
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TEST_SWR(0x71737c10, 0x800df660, 0x000002e6, 0x000002e4, 0x7c10C7D8, 0xA5B6C7D8)
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TEST_SWR(0x71737c10, 0x800df660, 0x000002e7, 0x000002e4, 0x10B6C7D8, 0xA5B6C7D8)
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TEST_SWR(0x03682420, 0x800d24e4, 0x00001680, 0x00001680, 0x03682420, 0xA5B6C7D8)
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TEST_SWR(0x03682420, 0x800d24e4, 0x00001681, 0x00001680, 0x682420D8, 0xA5B6C7D8)
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TEST_SWR(0x03682420, 0x800d24e4, 0x00001682, 0x00001680, 0x2420C7D8, 0xA5B6C7D8)
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TEST_SWR(0x03682420, 0x800d24e4, 0x00001683, 0x00001680, 0x20B6C7D8, 0xA5B6C7D8)
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TEST_SWR(0x6f59f5d3, 0x800dabdc, 0x000001b0, 0x000001b0, 0x6f59f5d3, 0xA5B6C7D8)
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TEST_SWR(0x6f59f5d3, 0x800dabdc, 0x000001b1, 0x000001b0, 0x59f5d3D8, 0xA5B6C7D8)
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TEST_SWR(0x6f59f5d3, 0x800dabdc, 0x000001b2, 0x000001b0, 0xf5d3C7D8, 0xA5B6C7D8)
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TEST_SWR(0x6f59f5d3, 0x800dabdc, 0x000001b3, 0x000001b0, 0xd3B6C7D8, 0xA5B6C7D8)
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###detect exception
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bne s2, zero, inst_error
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nop
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###score ++
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addiu s3, s3, 1
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###output (s0<<24)|s3
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inst_error:
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sll t1, s0, 24
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or t0, t1, s3
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sw t0, 0(s1)
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jr ra
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nop
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END(n93_swr_test)
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@ -2,7 +2,7 @@
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#include <regdef.h>
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#include <cpu_cde.h>
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|
||||
#define TEST_NUM 89
|
||||
#define TEST_NUM 93
|
||||
|
||||
|
||||
##s0, number
|
||||
@ -651,6 +651,22 @@ kseg0_kseg1:
|
||||
nop
|
||||
jal wait_1s
|
||||
nop
|
||||
jal n90_lwl_test
|
||||
nop
|
||||
jal wait_1s
|
||||
nop
|
||||
jal n91_lwr_test
|
||||
nop
|
||||
jal wait_1s
|
||||
nop
|
||||
jal n92_swl_test
|
||||
nop
|
||||
jal wait_1s
|
||||
nop
|
||||
jal n93_swr_test
|
||||
nop
|
||||
jal wait_1s
|
||||
nop
|
||||
###check io access
|
||||
LI (a0, IO_SIMU_ADDR)
|
||||
LI (t0, 0x1234)
|
||||
|
@ -59,9 +59,9 @@
|
||||
32'b100011?????????????????????????? 0 0 0 0 1 0 ? ALIGN 0 0 // LW
|
||||
32'b100100?????????????????????????? 0 0 0 0 1 0 0 ALIGN 0 0 // LBU
|
||||
32'b100101?????????????????????????? 0 0 0 0 1 0 0 ALIGN 0 0 // LHU
|
||||
32'h100110?????????????????????????? 0 0 0 0 1 0 ? URIGHT 1 0 // LWR
|
||||
32'b101000?????????????????????????? 0 0 0 0 1 1 ? ALIGN ? ? // SB
|
||||
32'b101001?????????????????????????? 0 0 0 0 1 1 ? ALIGN ? ? // SH
|
||||
32'b101010?????????????????????????? 0 0 0 0 1 1 ? ULEFT ? ? // SWL
|
||||
32'b101011?????????????????????????? 0 0 0 0 1 1 ? ALIGN ? ? // SW
|
||||
32'b101110?????????????????????????? 0 0 0 0 1 1 ? URIGHT ? ? // SWR
|
||||
32'h100110?????????????????????????? 0 0 0 0 1 0 ? URIGHT 1 ? // LWR
|
||||
32'b101000?????????????????????????? 0 0 0 0 1 1 ? ALIGN 0 0 // SB
|
||||
32'b101001?????????????????????????? 0 0 0 0 1 1 ? ALIGN 0 0 // SH
|
||||
32'b101010?????????????????????????? 0 0 0 0 1 1 ? ULEFT 0 1 // SWL
|
||||
32'b101011?????????????????????????? 0 0 0 0 1 1 ? ALIGN 0 0 // SW
|
||||
32'b101110?????????????????????????? 0 0 0 0 1 1 ? URIGHT 1 ? // SWR
|
Loading…
Reference in New Issue
Block a user